Devices having a semiconductor material that is semimetal in bulk and methods of forming the same

• US 9,564,493 B2
• Filed: 03/13/2015
• Issued: 02/07/2017
• Est. Priority Date: 03/13/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Colinge, Jean-Pierre, Diaz, Carlos H., Yeo, Yee-Chia
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Nguyen, Cuong B.
• Application Number:
  US14/656,948
• Publication Number:
  US 20160268382A1
• Time in Patent Office: 697 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/02598 monocrystalline
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/426 using masks
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/461 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/8256 the substrate being a semiconductor, using technologies not covered by one of groups H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252 and H01L21/8254 H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1207 : combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1222 : with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/127 : with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/04 : characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 : with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 : including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/267 : in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 : of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

Claims

1. A structure comprising:

a substrate having an upper surface;

a first source/drain contact region;

a channel structure connected to and over the first source/drain contact region, the channel structure being over the upper surface of the substrate, the channel structure having a sidewall extending above the first source/drain contact region, the channel structure comprising a bismuth-containing semiconductor material;

a gate dielectric along the sidewall of the channel structure;

a gate electrode along the gate dielectric; and

a second source/drain contact region connected to and over the channel structure.

2. The structure of claim 1, wherein the bismuth-containing semiconductor material is doped bismuth (Bi).

3. The structure of claim 1, wherein the channel structure has a cross section area in a plane parallel to the upper surface of the substrate, the cross section area having a largest dimension of 53 nm or less.

4. The structure of claim 1, wherein the bismuth-containing semiconductor material is doped with a p-type dopant.

5. The structure of claim 1, wherein the bismuth-containing semiconductor material is doped with an n-type dopant.

6. The structure of claim 1, wherein the bismuth-containing semiconductor material is monocrystalline.

7. The structure of claim 1, wherein the bismuth-containing semiconductor material does not have a p-n junction.

8. The structure of claim 1, wherein the first source/drain contact region is over the upper surface of the substrate, the first source/drain contact region comprising a substantially pure metal, a semiconductor-metal compound, or a combination thereof.

9. The structure of claim 1, wherein the substrate is a semiconductor substrate, the first source/drain contact region comprising a doped semiconductor region in the semiconductor substrate.

10. The structure of claim 1, wherein the substrate comprises:

a semiconductor substrate;

devices on the semiconductor substrate; and

interconnect structures on the semiconductor substrate, the interconnect structures comprising an upper dielectric layer, the upper surface of the substrate—

in contact with a surface of the upper dielectric layer.

11. A structure comprising:

a substrate comprising a horizontal surface, the horizontal surface being an upper surface of the substrate;

a first vertical channel transistor over the horizontal surface of the substrate, the first vertical channel transistor comprising;

a first source/drain contact region,

a first bismuth-containing channel structure connected to and over the first source/drain contact region, the first bismuth-containing channel structure being a semiconductor and comprising an n-type dopant, the first bismuth-containing channel structure extending perpendicular to the horizontal surface,

a first gate dielectric around the first bismuth-containing channel structure,

a first gate electrode around the first gate dielectric, the first gate dielectric being disposed between the first bismuth-containing channel structure and the first gate electrode, and

a second source/drain contact region connected to and over the first bismuth-containing channel structure; and

a second vertical channel transistor over the horizontal surface of the substrate, the second vertical channel transistor comprising;

a third source/drain contact region,

a second bismuth-containing channel structure connected to and over the third source/drain contact region, the second bismuth-containing channel structure being a semiconductor and comprising a p-type dopant, the second bismuth-containing channel structure extending perpendicular to the horizontal surface,

a second gate dielectric around the second bismuth-containing channel structure,

a second gate electrode around the second gate dielectric, the second gate dielectric being disposed between the second bismuth-containing channel structure and the second gate electrode, and

a fourth source/drain contact region connected to and over the second bismuth-containing channel structure.

12. The structure of claim 11, wherein a cross section of the first bismuth-containing channel structure in a plane parallel to the horizontal surface has a largest dimension 53 nm or less, and a cross section of the second bismuth-containing channel structure in a plane parallel to the horizontal surface has a largest dimension 53 nm or less.

13. The structure of claim 11, wherein the first bismuth-containing channel structure and the second bismuth-containing channel structure each comprise a monocrystalline bismuth-containing material.

14. The structure of claim 11, wherein the first source/drain contact region and the third source/drain contact region are over the horizontal surface of the substrate, the first source/drain contact region and the third source/drain contact region each comprising a substantially pure metal, a semiconductor-metal compound, or a combination thereof.

15. The structure of claim 11, wherein the substrate is a semiconductor substrate, the first source/drain contact region comprising an n-doped region in the semiconductor substrate, and the third source/drain contact region comprises a p-doped region in the semiconductor substrate.

16. The structure of claim 11, wherein the substrate comprises:

a semiconductor substrate;

devices on the semiconductor substrate; and

interconnect structures on the semiconductor substrate, the interconnect structures comprising an upper dielectric layer, the horizontal surface of the substrate—

in contact with a surface of the upper dielectric layer.

17. A structure comprising:

a substrate having an upper surface;

a first source/drain contact region;

a first channel structure connected to and over the first source/drain contact region, the first channel structure being over the upper surface of the substrate, the first channel structure having a first sidewall extending above the first source/drain contact region, the first channel structure comprising a first bismuth-containing semiconductor material;

a first gate dielectric along the first sidewall of the first channel structure;

a first gate electrode along the first gate dielectric;

a second source/drain contact region connected to and over the first channel structure;

a third source/drain contact region over the second source/drain contact region;

a second channel structure connected to and over the third source/drain contact region, the second channel structure having a second sidewall extending above the third source/drain contact region, the second channel structure comprising a second bismuth-containing semiconductor material;

a second gate dielectric along the second sidewall of the second channel structure; and

a second gate electrode along the second gate dielectric.

18. The structure of claim 17, further comprising an interconnect structure interposed between the second source/drain contact region and the third source/drain contact region.

19. The structure of claim 18, wherein the first gate electrode is electrically coupled to the third source/drain contact region.

20. The structure of claim 17, wherein the first and second bismuth-containing semiconductor materials comprise doped bismuth (Bi).