Self-aligned metal oxide thin-film transistor component and manufacturing method thereof

• US 9,564,536 B2
• Filed: 11/30/2012
• Issued: 02/07/2017
• Est. Priority Date: 11/26/2012
• Status: Active Grant

• Current Assignee: Shenzhen Royole Technologies Co. Ltd
• Original Assignee: Shenzhen Royole Technologies Co. Ltd
• Inventors: Wei, Peng, Yu, Xiaojun, Liu, Zihong
• Primary Examiner(s): Sandvik, Benjamin
• Assistant Examiner(s): ASSOUMAN, HERVE-LOUIS Y
• Application Number:
  US14/648,628
• Publication Number:
  US 20150303308A1
• Time in Patent Office: 1,530 Days
• Field of Search: 257/43
• US Class Current: 1/1
• CPC Class Codes: C12Q 1/6895 for plants, fungi or algae
• CPC Class Codes: C12Q 2600/156 Polymorphic or mutational markers
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present invention is applicable to the field of electronic component technologies and provides a manufacturing method of a self-aligned metal oxide TFT component, including: selecting a substrate and preparing a gate on the substrate; successively disposing an insulation layer, a transparent electrode layer, and a photoresist on the gate; using the gate as a mask to perform exposure from a back side of the substrate, so as to form a source and a drain that are aligned with the gate; depositing a metal oxide semiconductor layer on the transparent electrode layer; performing etching on the semiconductor layer, the source, and the drain, so that outer ends of the source and the drain are exposed out of the metal oxide semiconductor layer; and depositing a passivation layer and leading out the source and the drain. In the present invention, a transparent conductor is used as the electrode layer, and a bottom gate is used as a mask to perform back exposure, so as to perform etching on the source and the drain, thereby implementing a self-alignment between the source or the drain and the gate, effectively reducing parasitic capacitance, and improving component performance. The component is of a bottom-gate bottom-contact structure, and there is no need to manufacture an etch-stop layer, thereby simplifying a process, reducing use of a photolithographic mask, improving production efficiency, and improving an electrical property of the component.

Claims

1. A manufacturing method of a self-aligned metal oxide thin-film transistor component, comprising:

preparing a non-transparent gate on a substrate;

successively disposing an insulation layer, a transparent electrode layer, and a photoresist on the gate;

using the gate as a mask to perform exposure from a back side of the substrate, an exposed part of the transparent electrode layer is cured and kept, and a non-exposed part of the transparent electrode layer aligned with the gate is peeled off together with the photoresist, thereby removing the non-exposed part that is of the transparent electrode layer and aligned with the gate, so as to form a source and a drain that are aligned with the gate;

depositing a metal oxide semiconductor layer on the source and the drain;

performing etching on the metal oxide semiconductor layer, the source, and the drain, so that outer ends of the source and the drain are exposed out of an etched metal oxide semiconductor layer, and isolating a drain from a source of a different thin-film transistor component; and

depositing a passivation layer on the substrate, and leading the source and the drain out of the passivation layer.

2. The manufacturing method according to claim 1, wherein performing etching on the metal oxide semiconductor layer, the source, and the drain, so that outer ends of the source and the drain are exposed out of an etched metal oxide semiconductor layer, and isolating a drain from a source of a different thin-film transistor component includes:

using a gray-tone mask to perform photolithography once from a front side of the substrate, so that a patterned metal oxide semiconductor layer covers a part of the source and a part of the drain, and the outer ends of the source and the drain are exposed out of the metal oxide semiconductor layer, and isolating the drain from the source of the different thin-film transistor component.

3. The manufacturing method according to claim 2, wherein leading the source and the drain out of the passivation layer includes:

performing etching on the passivation layer, so as to form a via to a part of the source that is exposed out of the metal oxide semiconductor layer and a via to a part of the drain that is exposed out of the metal oxide semiconductor layer; and

depositing conducting materials into the vias, so as to form a conducting lead to lead out the source and the drain.

4. The manufacturing method according to claim 3, wherein the conducting materials are transparent conducting materials.

5. A manufacturing method of a self-aligned metal oxide thin-film transistor pixel circuit, comprising:

preparing a gate, a gate lead, and a storage capacitor electrode which are not transparent on a substrate;

successively disposing an insulation layer, a transparent electrode layer, and a photoresist on the gate, the gate lead, and the storage capacitor electrode;

using the gate, the gate lead, and the storage capacitor electrode as a mask to perform exposure from a back side of the substrate, an exposed part of the transparent electrode layer is cured and kept, and non-exposed parts of the transparent electrode layer aligned with the gate, the gate lead, and the storage capacitor electrode are peeled off together with the photoresist, thereby removing the non-exposed parts that are of the transparent electrode layer and aligned with the gate, the gate lead, and the storage capacitor electrode, so as to form a source and a drain that are aligned with the gate;

depositing a metal oxide semiconductor layer on the source, the drain, and the other reserved part of the transparent electrode layer;

performing etching on the metal oxide semiconductor layer, the source, and the drain, so that outer ends of the source and the drain are exposed out of an etched metal oxide semiconductor layer, and isolating a drain from a source of a different thin-film transistor component; and

depositing a passivation layer on the substrate, and leading the source, the drain, and the gate lead out of the passivation layer.

6. The manufacturing method according to claim 5, wherein performing etching on the metal oxide semiconductor layer, the source, and the drain, so that outer ends of the source and the drain are exposed out of an etched metal oxide semiconductor layer, and isolating a drain from a source of a different thin-film transistor component includes:

using a gray-tone mask plate to perform photolithography once from a front side of the substrate, and removing a part of the transparent electrode layer and a part of the metal oxide semiconductor layer that are of an area corresponding to the gate lead and the storage capacitor electrode, so that the outer ends of the source and the drain are exposed out of the etched metal oxide semiconductor layer, and isolating the drain from the source of the different thin-film transistor component.

7. The manufacturing method according to claim 6, wherein leading the source, the drain, and the gate lead out of the passivation layer includes:

performing etching on the passivation layer, so as to form a via to the gate lead, a via to a part of the source that is exposed out of the metal oxide semiconductor layer, and a part of the drain that is exposed out of the metal oxide semiconductor layer; and

depositing conducting materials into the vias, so as to form a conducting lead to lead out the source, the drain, and the gate lead.

8. The manufacturing method according to claim 7, wherein the conducting materials are transparent conducting materials.