Zero current detecting circuit and method and related synchronous switching power converter

• US 9,564,809 B2
• Filed: 09/01/2015
• Issued: 02/07/2017
• Est. Priority Date: 04/16/2015
• Status: Active Grant

• Current Assignee: Anpec Electronics Corporation
• Original Assignee: Anpec Electronics Corporation
• Inventors: Chen, Chih-Yuan, Yen, Tzu-Yang
• Primary Examiner(s): Mehari, Yemane
• Application Number:
  US14/842,813
• Publication Number:
  US 20160308441A1
• Time in Patent Office: 525 Days
• Field of Search: 323/223, 323/224, 323/235, 323/239, 323/240, 323282-284
• US Class Current: 1/1
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A zero current detecting circuit is disclosed. The zero current detecting circuit includes a first zero current comparator for determining current variation on an inductor of a synchronous switching power converter so as to output a zero current signal to turn off a down-bridge transistor of the synchronous power converter; a second zero current comparator for determining whether the first zero current comparator turns off the down-bridge transistor too early or too late and outputting a comparison result; a counter coupled to the second zero current comparator for ascending or descending a control bit according to the comparison result, and an adjustable delay unit coupled to the first zero current comparator and the counter for adjusting a delay time according to the control bit, and delaying and outputting the zero current signal according to the delay time, to compensate a negative offset voltage by delay.

Claims

1. A zero current detecting circuit, comprising:

a first zero current comparator for determining current variation on an inductor of a synchronous switching power converter so as to output a zero current signal to turn off a down-bridge transistor of the synchronous switching power converter;

a second zero current comparator for determining whether the first zero current comparator turns off the down-bridge transistor too early or too late, and outputting a comparison result;

a counter coupled to the second zero current comparator for ascending or descending a control bit according to the comparison result; and

an adjustable delay unit coupled to the first zero current comparator and the counter for adjusting a delay time according to the control bit, and delaying and outputting the zero current signal according to the delay time, to compensate a negative offset voltage by delay.

2. The zero current detecting circuit of claim 1, wherein the counter ascends the control bit when the comparison result is at a low level and descends the control bit when the comparison result is at a high level.

3. The zero current detecting circuit of claim 1, wherein the adjustable voltage source increases the delay time when the control bit is decreased and decreases the delay time when the control bit is increased.

4. The zero current detecting circuit of claim 1, wherein the first zero current comparator comprises:

a positive input terminal coupled to a first terminal of the down-bridge transistor for detecting current variation on the inductor;

a negative input terminal coupled to the negative offset voltage; and

an output terminal for outputting the zero current signal according to the current variation on the inductor and the negative offset voltage.

5. The zero current detecting circuit of claim 1, wherein the second zero current comparator comprises:

a positive input terminal coupled to a first terminal of the down-bridge transistor for detecting current variation on the inductor;

a negative input terminal coupled to a reference voltage; and

an output terminal coupled to the counter for outputting the comparison result to the counter according to the reference voltage and the current variation on the inductor.

6. A synchronous switching power converter with zero current detecting, comprising:

an up-bridge transistor comprising;

a first terminal coupled to an input power supply;

a second terminal; and

a third terminal for receiving a turned-on signal;

a down-bridge transistor comprising;

a first terminal coupled to a ground;

a second terminal coupled to the second terminal of the up-bridge transistor; and

a third terminal for receiving a turned-off signal;

an inductor coupled between the second terminal of the down-bridge transistor and an output capacitor; and

a zero current detecting circuit comprising;

a first zero current comparator for determining current variation on the inductor of a synchronous switching power converter so as to output a zero current signal to turn off a down-bridge transistor of the synchronous switching power converter;

a second zero current comparator for determining whether the first zero current comparator turns off the down-bridge transistor too early or too late and outputting a comparison result;

a counter coupled to the second zero current comparator for ascending or descending a control bit according to the comparison result; and

an adjustable delay unit coupled to the first zero current comparator and the counter for adjusting an delay time according to the control bit, and delaying and outputting the zero current signal according to the delay time, to compensate a negative offset voltage by delay.

7. The synchronous switching power converter of claim 6, wherein the counter ascends the control bit when the comparison result is at a low level and descends the control bit when the comparison result is at a high level.

8. The synchronous switching power converter of claim 6, wherein the adjustable voltage source increases the delay time when the control bit is decreased and decreases the delay time when the control bit is increased.

9. The synchronous switching power converter of claim 6, wherein the first zero current comparator comprises:

a positive input terminal coupled to a first terminal of the down-bridge transistor for detecting the current variation on the inductor;

a negative input terminal coupled to the negative offset voltage; and

an output terminal for outputting the zero current signal according to the current variation on the inductor and the negative offset voltage to turn off the down-bridge transistor.

10. The synchronous switching power converter of claim 6, wherein the second zero current comparator comprises:

a positive input terminal coupled to a first terminal of the down-bridge transistor for detecting the current variation on the inductor;

a negative input terminal coupled to a reference voltage; and

an output terminal coupled to the counter for outputting the comparison result to the counter according to the reference voltage and the current variation on the inductor.

11. A zero current detecting method for a synchronous switching power converter, comprising:

determining current variation on an inductor of a synchronous switching power converter to output a zero current signal to turn off a down-bridge transistor of the synchronous switching power converter;

determining whether the down-bridge transistor is turned off too early or too late and outputting a comparison result;

ascending or descending a control bit according to the comparison result; and

adjusting a delay time according to the control bit, and delaying and outputting the zero current signal according to the delay time, to compensate a negative offset voltage by delay.

12. The zero current detecting method of claim 11, wherein ascending the control bit when the comparison result is at a low level and descending the control bit when the comparison result is at a high level.

13. The zero current detecting method of claim 11, further comprising increasing the delay time when the control bit is decreased and decreasing the delay time when the control bit is increased.