Fault tolerant chip-to-chip communication with advanced voltage

• US 9,564,994 B2
• Filed: 09/26/2014
• Issued: 02/07/2017
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin, Ulrich, Roger
• Primary Examiner(s): Gidado, Rasheed
• Application Number:
  US14/498,957
• Publication Number:
  US 20150092532A1
• Time in Patent Office: 865 Days
• US Class Current: 1/1
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0035 evaluation of received explicit signalling
• CPC Class Codes: H04L 1/0056 Systems characterized by the type of code used H04L1/08 takes precedence

Abstract

Systems and circuits are described for transmitting data over physical channels to provide a fault tolerant, high speed, low latency interface such as between a memory controller and memory devices. Communications signals are communicated over interconnection groups comprised of multiple wires, with the described encoding and decoding permitting continued communication in the presence of a wire failure within an interconnection group. An efficient distributable voltage regulator to provide communications driver power is also disclosed.

Claims

1. A system for data communications over a multiple signal wire communications channel, the system comprising:

a fault detector configured to identify at least one failed signal wire from a plurality of wires of the communications channel, and to generate a set of indices identifying unbroken wires of the communications channel; and

an encoder configured to receive a plurality of data bits and the set of indices identifying unbroken wires, and to transition a subset of the unbroken wires according to at least one transition-limiting function operating on a previous state of the subset of the unbroken wires and a subset of the plurality of data bits, the subset of the unbroken wires identified by one or more indices of the set of indices.

2. The system of claim 1, wherein the fault detector operates at system initialization.

3. The system of claim 1, wherein the plurality of data bits comprises three bits, and the communications channel comprises four signal wires including one failed signal wire and three unbroken wires.

4. The system of claim 1, wherein the plurality of data bits comprises four bits, and the communications channel comprises four signal wires including one failed signal wire and three unbroken wires.

5. The system of claim 1, further comprising a voltage regulator configured to set the signal level of at least one signal of the group of signals.

6. The system of claim 5, wherein the voltage regulator comprises at least one charge pump or current source controlled by the plurality of data bits.

7. The system of claim 6, wherein the voltage regulator further comprises at least one charge pump or current source controlled by a measurement of the regulated voltage output.

8. The system of claim 1, wherein the at least one transition-limiting function comprises a single transition-limiting function.

9. The system of claim 8, wherein the encoder is configured to check a first bit of the plurality of bits for a first condition that:

if satisfied, transitions a pair of unbroken wires according to the single transition-limiting function; and

if the first condition fails, the encoder is configured to check all remaining bits of the plurality of bits for a second condition that if satisfied, transitions a single unbroken wire according to the single transition-limiting function.

10. The system of claim 1, wherein the at least one transition-limiting function comprises a first transition limiting function and a second transition-limiting function.

11. The system of claim 10, wherein the encoder is configured to check a first pair of bits for a first condition that:

if satisfied, transitions a pair of unbroken wires according to a first transition-limiting function, and

if the first condition fails, the encoder is configured to check a second pair of bits for a second condition, the second pair of bits different than the first pair of bits, wherein if the second condition is satisfied, the encoder transitions a single unbroken wire according to a second transition-limiting function.

12. A method comprising:

receiving a plurality of data bits;

identifying at least one failed signal wire from a plurality of wires of a communications channel, responsively generating a set of indices identifying unbroken wires of the communications channel; and

,

transitioning a subset of the unbroken wires according to at least one transition-limiting function operating on a previous state of the subset of the unbroken wires and a subset of the plurality of data bits, the subset of the unbroken wires identified by one or more indices of the set of indices.

13. The method of claim 12, wherein the plurality of data bits comprises three bits, and the communications channel comprises four signal wires including one failed signal wire and three unbroken wires.

14. The method of claim 12, wherein the plurality of data bits comprises four bits, and the communications channel comprises four signal wires including one failed signal wire and three unbroken wires.

15. The method of claim 12, further comprising setting a signal level of at least one signal of the group of signals using a voltage regulator.

16. The method of claim 12, wherein the at least one transition-limiting function is implemented using a lookup table (LUT).

17. The method of claim 12, wherein the at least one transition-limiting function comprises a single transition-limiting function.

18. The method of claim 17, further comprising checking a first bit of the plurality of bits for a first condition that:

if satisfied, transitioning a pair of unbroken wires according to the single transition-limiting function; and

if the first condition fails, checking all remaining bits of the plurality of bits for a second condition that if satisfied, transitioning a single unbroken wire according to the single transition-limiting function.

19. The method of claim 12, wherein the at least one transition-limiting function comprises a first transition limiting function and a second transition-limiting function.

20. The method of claim 19, further comprising checking a first pair of bits for a first condition, and if the first condition is satisfied, transitioning a pair of unbroken wires according to a first transition-limiting function, and

if the first condition fails, checking a second pair of bits for a second condition, and if the second condition is satisfied, transitioning a single unbroken wire according to a second transition-limiting function.