Techniques for adjusting clock signals to compensate for noise
First Claim
1. A system comprising:
- a first integrated circuit chip comprisinga first internal clock buffer circuit, which draws current that is sourced from a first supply voltage, the first internal clock buffer circuit to provide a first internal clock signal that exhibits first power supply induced jitter (PSIJ) based on the first supply voltage, anda first interface circuit to output data synchronously with respect to the first internal clock signal;
a second integrated circuit chip comprisinga supply voltage node that receives the first supply voltage from the first integrated circuit chip,a second internal clock buffer circuit, which draws current from the supply voltage node that is sourced from the first supply voltage, the second internal clock buffer circuit to generate a second internal clock signal that exhibits second PSIJ based on the first supply voltage, anda second interface circuit to receive the data synchronously with respect to the second internal clock signal; and
wherein the second PSIJ compensates for timing error that is based on the first PSIJ.
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Accused Products
Abstract
A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.
153 Citations
26 Claims
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1. A system comprising:
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a first integrated circuit chip comprising a first internal clock buffer circuit, which draws current that is sourced from a first supply voltage, the first internal clock buffer circuit to provide a first internal clock signal that exhibits first power supply induced jitter (PSIJ) based on the first supply voltage, and a first interface circuit to output data synchronously with respect to the first internal clock signal; a second integrated circuit chip comprising a supply voltage node that receives the first supply voltage from the first integrated circuit chip, a second internal clock buffer circuit, which draws current from the supply voltage node that is sourced from the first supply voltage, the second internal clock buffer circuit to generate a second internal clock signal that exhibits second PSIJ based on the first supply voltage, and a second interface circuit to receive the data synchronously with respect to the second internal clock signal; and wherein the second PSIJ compensates for timing error that is based on the first PSIJ. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A first integrated circuit chip comprising:
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a first clock buffer circuit, which draws current that is sourced from a first supply voltage, the first clock buffer circuit to provide a first internal clock signal that exhibits first power supply induced jitter (PSIJ) that is based on the first supply voltage; an interface circuit to output data to a second integrated circuit chip, synchronously with respect to the first internal clock signal, wherein the second integrated circuit chip receives the data synchronously with respect to a second internal clock signal and receives the first supply voltage provided by the first integrated circuit, wherein the second internal clock signal exhibits second PSIJ that is based on the first supply voltage and is generated by a second clock buffer circuit, which draws current that is sourced from the first supply voltage; and wherein the second PSIJ compensates for timing error that is based on the first PSIJ. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A first integrated circuit chip comprising:
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a first clock buffer circuit, which draws current that is sourced from a first supply voltage, the first clock buffer circuit to provide a first internal clock signal that exhibits first power supply induced jitter (PSIJ) based on the first supply voltage; a supply voltage terminal to provide the first supply voltage to a second integrated circuit chip; an interface circuit to receive data from the second integrated circuit chip, synchronously with respect to the first internal clock signal, wherein the second integrated circuit chip transmits the data to the first integrated circuit chip synchronously with respect to a second internal clock signal that exhibits second power supply induced jitter (PSIJ), wherein the second internal clock signal is generated by a second clock buffer circuit, which draws current that is sourced from the first supply voltage, wherein the second PSIJ is based on the first supply voltage; and wherein the second PSIJ compensates for timing error that is based on the first PSIJ. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A method of operation of a first integrated circuit chip, the method comprising:
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drawing current in a first clock buffer circuit to provide a first internal clock signal exhibiting first power supply induced jitter (PSIJ), wherein the current is sourced from a first supply voltage and the first PSIJ is based on the first supply voltage; providing the first supply voltage to a second integrated circuit chip; receiving data from the second integrated circuit chip, synchronously with respect to the first internal clock signal, wherein the second integrated circuit chip transmits the data to the first integrated circuit chip synchronously with respect to a second clock signal that exhibits second PSIJ, wherein the second clock signal is derived from an external timing signal and is generated by a second clock buffer circuit, which draws current that is sourced from the first supply voltage, the second PSIJ being based on the first supply voltage; and wherein the second PSIJ compensates for timing error that is based on the first PSIJ. - View Dependent Claims (22, 23, 24, 25, 26)
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Specification