General input/output architecture, protocol and related methods to implement flow control

• US 9,565,106 B2
• Filed: 12/31/2013
• Issued: 02/07/2017
• Est. Priority Date: 08/24/2001
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ajanovic, Jasmin, Harriman, David, Fanning, Blaise, Lee, David M.
• Primary Examiner(s): Baturay, Alicia
• Application Number:
  US14/145,384
• Publication Number:
  US 20140185436A1
• Time in Patent Office: 1,134 Days
• Field of Search: 709/234
• US Class Current: 1/1
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4252 using a handshaking protocol
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 13/4269 using a handshaking protocol, e.g. Centronics connection
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes

Abstract

A storage device is provided to maintain a value of flow control credits allocated for a device on a channel and flow control logic is provided to receive a flow control signal over a link of an interconnect, the flow control signal indicating flow control credits allocated for the device on the channel. The flow control logic is further to update the value of flow control credits based on activity of the device on the channel.

Claims

1. An apparatus comprising:

a storage device to;

maintain a value of flow control credits allocated for a device on a particular one of a plurality of virtual channels, wherein each of the plurality of virtual channels has a corresponding virtual channel type and the virtual channel types comprise a request-type virtual channel and a response-type virtual channel; and

flow control logic to;

receive a flow control signal over a link of an interconnect, wherein the flow control signal indicates flow control credits allocated for the device on the particular virtual channels, wherein respective flow control credits are to be allocated for each of the plurality of virtual channels, and the interconnect comprises a cache coherent interconnect; and

update the value of flow control credits based on activity of the device on the particular virtual channel.

2. The apparatus of claim 1, wherein the interconnect comprises a coherent interconnect.

3. The apparatus of claim 1, wherein the flow control signal is received in association with a reset of the link.

4. The apparatus of claim 3, wherein the reset of the link comprises an initialization of the particular virtual channel.

5. The apparatus of claim 4, wherein the logic is to maintain a value of flow control credits consumed since initialization of the particular virtual channel.

6. The apparatus of claim 5, wherein the activity is to comprise sending data on the particular virtual channel to another device.

7. The apparatus of claim 6, wherein the logic is further to determine whether to send data on the particular virtual channel based at least in part on the value of consumed flow control credits.

8. The apparatus of claim 1, wherein the activity is to comprise sending data on the particular virtual channel to another device.

9. The apparatus of claim 8, wherein the data is to be delayed when insufficient flow control credits exist for the particular virtual channel.

10. The apparatus of claim 9, wherein the sending of the data is to be blocked when insufficient flow control credits exist for the particular virtual channel and the logic is to retry the sending of the data following the data being blocked.

11. The apparatus of claim 1, wherein the plurality of virtual channels includes at least four virtual channels.

12. An apparatus comprising:

a storage medium to maintain a value to indicate a count of allocated flow control credits that remain for a device on a particular one of a plurality of virtual channels, wherein the value is to be updated based on activity of the device on the particular virtual channel, the activity includes data sent on the particular virtual channel by the device, each of the plurality of virtual channels has a corresponding virtual channel type, and the virtual channel types comprise a request-type virtual channel and a response-type virtual channel; and

flow control logic to;

receive a flow control signal over a link of a cache coherent interconnect, wherein the flow control signal is to indicate the flow control credits allocated for the device on the particular virtual channel, the flow control credits are to be allocated following a reset of the link, and respective flow control credits are to be allocated for each of the plurality of virtual channels, and

cause data sent on the virtual channel to be retried based on an indication that insufficient flow control credits are allocated for the device on the virtual channel.

13. A method comprising:

receiving a flow control signal over a link of a cache coherent interconnect, wherein the flow control signal indicates flow control credits allocated for a device on a particular one of a plurality of virtual channels, wherein each of the plurality of virtual channels has a corresponding virtual channel type and the virtual channel types comprise a request-type virtual channel and a response-type virtual channel;

maintaining a value of flow control credits allocated for the device on the particular virtual channel, wherein respective flow control credits are to be allocated for each of the plurality of virtual channels;

identifying data transmitted on the particular virtual channel by the device; and

updating the value of flow control credits based on the data transmitted on the particular virtual channel.

14. The method of claim 13, further comprising attempting to send particular data on the particular virtual channel.

15. The method of claim 14, further comprising identifying that the attempt to send the particular data is blocked based on insufficient flow control credits on the particular virtual channel.

16. The method of claim 15, further comprising retrying the sending of the particular data.

17. A system comprising:

an interconnect;

a first device; and

a second device communicatively coupled to the first device using the interconnect, the second device comprising logic to;

receive a flow control signal over a link of a cache coherent interconnect, wherein the flow control signal indicates flow control credits allocated for a device on a particular one of a plurality of virtual channels, wherein each of the plurality of virtual channels has a corresponding virtual channel type and the virtual channel types comprise a request-type virtual channel and a response-type virtual channel;

maintain a value of flow control credits allocated for the device on the particular virtual channel, wherein respective flow control credits are to be allocated for each of the plurality of virtual channels; and

update the value of flow control credits based on activity of the device on the particular virtual channel.

18. The system of claim 17, wherein the interconnect comprises a coherent interconnect fabric.

19. The system of claim 17, wherein the device comprises an endpoint.

20. The system of claim 17, wherein the second device comprises a switch.

21. The system of claim 17, wherein the second device comprises a root complex.