Detection device, sensor, electronic apparatus and moving object

• US 9,568,315 B2
• Filed: 12/09/2014
• Issued: 02/14/2017
• Est. Priority Date: 12/10/2013
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Il, Naoki, Maki, Katsuhiko, Kurashina, Takashi
• Primary Examiner(s): Patel, Harshad R
• Assistant Examiner(s): Shah, Samir M
• Application Number:
  US14/564,554
• Publication Number:
  US 20150160012A1
• Time in Patent Office: 798 Days
• US Class Current: 1/1
• CPC Class Codes: G01C 19/5614 Signal processing
• CPC Class Codes: G01C 19/5776 Signal processing not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719
• CPC Class Codes: G01D 5/12 using electric or magnetic means G01D5/06 takes precedence
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means

Abstract

A detection device includes a drive circuit of a physical quantity transducer, a synchronization signal output circuit, and a detection circuit that performs detection of a physical quantity signal based on a physical quantity. The synchronization signal output circuit includes a delay locked loop (DLL) circuit that includes: a delay control circuit that outputs a delay control signal and a delay circuit that includes a plurality of delay units in which a delay time is controlled by the delay control signal; an adjustment circuit that includes at least one delay unit in which a delay time is controlled by the delay control signal, and outputs a signal obtained by delaying an input signal based on the output signal from the drive circuit to the DLL circuit; and an output circuit that outputs the synchronization signal based on multi-phase clock signals from the DLL circuit.

Claims

1. A detection device comprising:

a drive circuit that receives a feedback signal from a physical quantity transducer and drives the physical quantity transducer;

a synchronization signal output circuit that receives an output signal from the drive circuit and outputs a synchronization signal; and

a detection circuit that performs detection of a physical quantity signal corresponding to a physical quantity based on a signal from the physical quantity transducer and the synchronization signal and outputs detection data,

wherein the synchronization signal output circuit includes;

a delay locked loop circuit that includes;

a delay control circuit that outputs a delay control signal, and

a delay circuit that includes a plurality of delay units in which a delay time is controlled by the delay control signal,

an adjustment circuit that includes at least one delay unit in which a delay time is controlled by the delay control signal, and outputs a signal obtained by delaying an input signal based on the output signal from the drive circuit to the delay locked loop circuit, and

an output circuit that outputs the synchronization signal based on multi-phase clock signals from the delay locked loop circuit.

2. The detection device according to claim 1,

wherein the adjustment circuit includes a second delay circuit that is configured by a delay unit having a delay time shorter than that of each of the plurality of delay units that form the delay circuit of the delay locked loop circuit.

3. A sensor comprising:

the detection device according to claim 2; and

the physical quantity transducer.

4. An electronic apparatus comprising the detection device according to claim 2.

5. A moving object comprising the detection device according to claim 2.

6. The detection device according to claim 1,

wherein the adjustment circuit includes another delay circuit configured by fewer delay units that the plurality of delay units that form the delay circuit of the delay locked loop circuit.

7. The detection device according to claim 1,

wherein the output circuit outputs the synchronization signal based on m multi-phase clock signals among n multi-phase clock signals from the delay locked loop circuit, m and n are integers larger than 1, and m is less than n.

8. The detection device according to claim 1,

wherein the output circuit includes:

a first selector that receives a first multi-phase clock signal group among the multi-phase clock signals from the delay locked loop circuit and outputs a first signal,

a second selector that receives a second multi-phase clock signal group among the multi-phase clock signals from the delay locked loop circuit and outputs a second signal, and

a third selector that receives the first signal and the second signal, and outputs the synchronization signal.

9. The detection device according to claim 1,

wherein the output circuit includes:

a first selector that receives a first multi-phase clock signal group among the multi-phase clock signals from the delay locked loop circuit and outputs a first signal,

a second selector that receives a second multi-phase clock signal group among the multi-phase clock signals from the delay locked loop circuit and outputs a second signal, and

a waveform shaping circuit that outputs the synchronization signal having a falling edge set by the first signal and a rising edge set by the second signal.

10. The detection device according to claim 9,

wherein the output circuit further includes:

a third selector that receives a third multi-phase clock signal group among the multi-phase clock signals from the delay locked loop circuit and outputs a third signal,

a fourth selector that receives a fourth multi-phase clock signal group among the multi-phase clock signals from the delay locked loop circuit and outputs a fourth signal, and

a second waveform shaping circuit that outputs a second synchronization signal having a falling edge set by the third signal and a rising edge set by the fourth signal.

11. The detection device according to claim 1,

wherein the delay control circuit compares phases of an input signal and an output signal of the delay locked loop circuit to generate the delay control signal.

12. The detection device according to claim 1,

wherein the delay control circuit performs phase comparison of j multi-phase clock signals among n multi-phase clock signals of the delay locked loop circuit to generate the delay control signal, n and j are integers larger than 1, and j is less than n.

13. The detection device according to claim 1,

wherein each delay unit that forms the delay locked loop circuit and the adjustment circuit is a differential circuit having a differential input and a differential output.

14. The detection device according to claim 1,

wherein a second direction is orthogonal to a first direction,

a third direction is opposite to the first direction,

a first delay unit group among the plurality of delay units of the delay locked loop circuit is arranged so that a direction from an input side of each delay unit to an output side thereof is along the first direction, and

a second delay unit group subsequent to the first delay unit group is arranged on the second direction side of the first delay unit group, and is arranged so that a direction from an input side of each delay unit to an output side thereof is along the third direction.

15. A sensor comprising:

the detection device according to claim 1; and

the physical quantity transducer.

16. An electronic apparatus comprising the detection device according to claim 1.

17. A moving object comprising the detection device according to claim 1.

18. A detection device comprising:

a drive circuit that receives a feedback signal from a physical quantity transducer and drives the physical quantity transducer;

a synchronization signal output circuit that receives an output signal from the drive circuit and outputs a synchronization signal; and

a detection circuit that performs detection of a physical quantity signal corresponding to a physical quantity based on a signal from the physical quantity transducer and the synchronization signal and outputs detection data,

wherein the synchronization signal output circuit includes;

a delay locked loop circuit that includes;

a delay control circuit that outputs a delay control signal, and

a delay circuit that includes a plurality of delay units in which a delay time is controlled by the delay control signal,

an adjustment circuit that includes at least one delay unit in which a delay time is controlled by the delay control signal, wherein the adjustment circuit is provided outside a loop of the delay locked loop circuit, and adjusts a phase of the synchronization signal, and

an output circuit that outputs the synchronization signal based on multi-phase clock signals from the delay locked loop circuit.