Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping

• US 9,568,548 B1
• Filed: 10/14/2015
• Issued: 02/14/2017
• Est. Priority Date: 10/14/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Franch, Robert L., Restle, Phillip J., Shan, David Wen-Hao
• Primary Examiner(s): O'Neill, Patrick
• Application Number:
  US14/882,668
• Time in Patent Office: 489 Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence

Abstract

A delay measurement technique using a tapped delay line edge capture circuit that captures tap position of edges within the delay line provides accuracy of measurement to one pico-second and below. A control circuit causes latches to capture an edge of a signal delayed through the delay line at taps of the delay line. The frequency of a clock from which the signal is derived is adjusted and tap outputs are captured by latches and averaged. A first frequency is found at which the average edge position is midway between two adjacent tap positions. A second signal, which may be the reference signal that clocks the latches, is propagated through the delay line and a second frequency is found for which the average edge position lies at the boundary between the two tap positions. The delay is determined from the difference between the periods of the first frequency and the second frequency.

Claims

1. A system for measuring a delay of an edge of a first signal with respect to an edge of a second signal, comprising:

an integrated circuit having a tapped delay circuit, wherein the edge of the first signal to be measured and the edge of the second signal to be measured are propagated through the tapped delay circuit and first tap positions of the edge of the first signal to be measured and second tap positions of the edge of the second signal to be measured are captured;

a test system that repeatedly sets a frequency of a clock signal of the integrated circuit from which the first signal and the second signal are synchronously derived to a plurality of measurement frequencies, wherein the test system reads an interface of the integrated circuit to read data from the integrated circuit corresponding to the first tap positions and the second tap positions, wherein the test system sets the frequency of the clock signal to a first frequency at which an average of the first tap positions lies at a boundary between a pair of adjacent tap positions and a second frequency at which an average of the second tap positions lies at the boundary between the pair of adjacent tap positions, and computes the delay from a difference between a period of the first frequency and a period of the second frequency.

2. The system of claim 1, wherein the first signal is a signal to be measured and the second signal is a reference clock provided to the tapped delay circuit to trigger the capture of the first tap positions.

3. The system of claim 2, wherein the tapped delay circuit further captures third tap positions of an edge of a third signal to be measured that is propagated through the tapped delay line, and wherein the test system further reads an interface of the integrated circuit to read data from the integrated circuit corresponding to the third tap positions, wherein the test system sets the frequency of the clock signal to a third frequency at which an average of the third tap positions lies at the boundary between the pair of adjacent tap positions and computes the a delay of the third signal from a difference between a period of the third frequency and a period of the second frequency.

4. The system of claim 3, wherein the tapped delay circuit comprises two tapped delays that capture the first and third tap positions simultaneously using corresponding ones of the two tapped delays.

5. The system of claim 1, wherein the clock signal of the integrated circuit is derived from an externally supplied clock, and wherein the test system sets a frequency of the externally supplied clock.

6. The system of claim 1, wherein the test system sets a frequency multiplier or divider within the integrated circuit that determines the frequency of the clock signal.

7. The system of claim 1, wherein the integrated circuit has a clock distribution network that operates in both non-resonant and resonant modes, wherein the first signal is a first clock generated in a non-resonant clocking mode of the integrated circuit, wherein the second signal to be measured is a second clock generated in a resonant clocking mode of the integrated circuit, and wherein the test system determines a latency of the first clock with respect to the second clock.

8. A system for measuring, comprising:

an integrated circuit having a tapped delay circuit, wherein the edge of the first signal to be measured and the edge of the second signal to be measured are propagated through the tapped delay circuit and first tap positions of the edge of the first signal to be measured and second tap positions of the edge of the second signal to be measured are captured at an edge of a reference clock signal;

a clock generator for generating an external clock supplied to the integrated circuit, wherein the reference clock signal is generated from an internal clock derived from the external clock; and

a test system that repeatedly sets a frequency of a clock signal of the integrated circuit from which the first signal and the second signal are synchronously derived to a plurality of measurement frequencies, wherein the test system reads an interface of the integrated circuit to read data from the integrated circuit corresponding to the first tap positions and the second tap positions, wherein the test system sets the frequency of the clock signal to a first frequency at which an average of the first tap positions lies at a boundary between a pair of adjacent tap positions and a second frequency at which an average of the second tap positions lies at the boundary between the pair of adjacent tap positions, and computes the delay from a difference between a period of the first frequency and a period of the second frequency.

9. The system of claim 8, wherein the first signal is a signal to be measured and the second signal is the reference clock signal.

10. The system of claim 9, wherein the tapped delay circuit further captures third tap positions of an edge of a third signal to be measured that is propagated through the tapped delay line, and wherein the test system further reads an interface of the integrated circuit to read data from the integrated circuit corresponding to the third tap positions, wherein the test system sets the frequency of the clock signal to a third frequency at which an average of the third tap positions lies at the boundary between the pair of adjacent tap positions and computes the a delay of the third signal from a difference between a period of the third frequency and a period of the second frequency.

11. The system of claim 9, wherein the tapped delay circuit comprises two tapped delays that capture the first and third tap positions simultaneously using corresponding ones of the two tapped delays.

12. The system of claim 8, wherein the test system further sets a frequency multiplier or divider within the integrated circuit that further determines the frequency of the reference clock signal.

13. The system of claim 8, wherein the integrated circuit has a clock distribution network that operates in both non-resonant and resonant modes, wherein the first signal is a first clock generated in a non-resonant clocking mode of the integrated circuit, wherein the second signal to be measured is a second clock generated in a resonant clocking mode of the integrated circuit, and wherein the test system determines a latency of the first clock with respect to the second clock.