Memory controller, memory system including the same and method of operating memory controller

• US 9,568,941 B2
• Filed: 01/05/2015
• Issued: 02/14/2017
• Est. Priority Date: 03/11/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jung, Jin-Su
• Primary Examiner(s): Chen, Xuxing
• Application Number:
  US14/589,660
• Publication Number:
  US 20150261250A1
• Time in Patent Office: 771 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory controller includes a clock scaler, a bus component and a level monitor. The clock scaler is configured to receive a first clock signal and configured to generate a second clock signal based on the first clock signal, first and second frequency control signals. A frequency of the second clock signal may increase based on the first frequency control signal and decrease based on the second frequency control signal. The bus component may operate based on the second clock signal and generate a level signal corresponding to a current operating state of the bus component. The level monitor may generate the first and second frequency control signals based on the level signal, a first threshold value, a second threshold value, a first reference time, and a second reference time.

Claims

1. A memory controller comprising:

a clock scaler configured to receive a first clock signal, a first frequency control signal, and a second frequency control signal and configured to generate a second clock signal based on the first clock signal, the first frequency control signal, and the second frequency control signal, a frequency of the second clock signal being configured to increase based on the first frequency control signal, and the frequency of the second clock signal being configured to decrease based on the second frequency control signal;

a bus component configured to operate based on the second clock signal and to generate a level signal corresponding to a current operating state of the bus component; and

a level monitor configured to generate the first frequency control signal and the second frequency control signal based on the level signal, a result of comparison between a first reference time and a time period during which a value of the level signal is greater than a first threshold value, and a result of comparison between a second reference time and a time period during which the value of the level signal is less than a second threshold value.

2. The memory controller of claim 1, wherein the frequency of the second clock signal is controlled based on a feedback operation and an aging operation, the feedback operation indicating that the frequency of the second clock signal is changed by determining the current operating state of the bus component based on the level signal, and the aging operation indicating that the frequency of the second clock signal is changed after either the first reference time or the second reference time has elapsed.

3. The memory controller of claim 1, wherein the level monitor includes:

a storage;

a comparator configured to generate a first comparison signal by comparing the level signal with the first threshold value and to generate a second comparison signal by comparing the level signal with the second threshold value; and

at least one controller configured to selectively activate the first frequency control signal based on the first comparison signal and the first reference time, and configured to selectively activate the second frequency control signal based on the second comparison signal and the second reference time.

4. The memory controller of claim 3, wherein the comparator is configured to activate the first comparison signal when the value of the level signal is greater than the first threshold value, and configured to activate the second comparison signal when the value of the level signal is less than the second threshold value.

5. The memory controller of claim 4, wherein the at least one controller is configured to activate the first frequency control signal when a first activation time is longer than the first reference time, the first activation time indicating a time during which the first comparison signal is activated.

6. The memory controller of claim 5, wherein the at least one controller includes a timer configured to measure the first activation time.

7. The memory controller of claim 4, wherein the at least one controller is configured to activate the second frequency control signal when a second activation time is longer than the second reference time, the second activation time indicating a time during which the second comparison signal is activated.

8. The memory controller of claim 3, wherein the storage is configured to store the first threshold value, the second threshold value, the first reference time, and the second reference time.

9. The memory controller of claim 1, wherein the bus component includes at least one request buffer, and the level signal has a value corresponding to an amount of requests that are currently received by the at least one request buffer.

10. The memory controller of claim 1, wherein the bus component includes at least one data buffer, and the level signal has a value corresponding to an amount of data that are currently received by the at least one data buffer.

11. The memory controller of claim 1, wherein at least one from among the first threshold value, the second threshold value, the first reference time, and the second reference time is variable.

12. The memory controller of claim 1, wherein at least one from among the first threshold value, the second threshold value, the first reference time, and the second reference time is determined based on a user input signal.

13. The memory controller of claim 1, wherein at least one from among the first threshold value, the second threshold value, the first reference time, and the second reference time is adaptively changed based on a training operation.

14. The memory controller of claim 1, wherein the memory controller is a direct memory access (DMA) controller.

15. A memory system comprising:

at least one memory device configured to store data; and

a memory controller configured to control an operation of the at least one memory device, the memory controller comprising;

a clock scaler configured to receive a first clock signal, a first frequency control signal, and a second frequency control signal and to configured generate a second clock signal based on the first clock signal, the first frequency control signal, and the second frequency control signal, a frequency of the second clock signal being configured to increase based on the first frequency control signal, and the frequency of the second clock signal being configured to decrease based on the second frequency control signal;

a bus component configured to operate based on the second clock signal and to generate a level signal corresponding to a current operating state of the bus component; and

a level monitor configured to generate the first frequency control signal and the second frequency control signal based on the level signal, a first threshold value, a second threshold value, a first reference time, and a second reference time, the level monitor including a storage, a comparator, and at least one controller,

wherein the comparator of the level monitor is configured to generate a first comparison signal by comparing the level signal with the first threshold value and to generate a second comparison signal by comparing the level signal with the second threshold value, and

the at least one controller is configured to selectively activate the first frequency control signal based on the first comparison signal and the first reference time, and configured to selectively activate the second frequency control signal based on the second comparison signal and the second reference time.

16. A method of operating a memory controller, the method comprising:

receiving a first clock signal by the memory controller;

generating by the memory controller a second clock signal based on the first clock signal;

operating a bus component included in the memory controller based on the second clock signal;

generating by the memory controller a first frequency control signal and a second frequency control signal based on a level signal, a result of comparison between a first reference time and a time period during which a value of the level signal is greater than a first threshold value, and a result of comparison between a second reference time and a time period during which the value of the level signal is less than a second threshold value, wherein the level signal corresponds to a current operating state of the bus component; and

changing by the memory controller a frequency of the second clock signal based on the first frequency control signal and the second frequency control signal.

17. The method of claim 16, wherein the generating the first and second frequency control signals includes:

generating a first comparison signal by comparing the level signal with the first threshold value;

generating a second comparison signal by comparing the level signal with the second threshold value;

selectively activating the first frequency control signal based on the first comparison signal and the first reference time; and

selectively activating the second frequency control signal based on the second comparison signal and the second reference time.

18. The method of claim 17, wherein the first comparison signal is activated when the value of the level signal is greater than the first threshold value, and

the second comparison signal is activated when the value of the level signal is smaller than the second threshold value.

19. The method of claim 18, wherein the first frequency control signal is activated when a first activation time is longer than the first reference time, the first activation time indicating a time during which the first comparison signal is activated, and

the second frequency control signal is activated when a second activation time is longer than the second reference time, the second activation time indicating a time during which the second comparison signal is activated.

20. The method of claim 19, wherein the frequency of the second clock signal increases when the first frequency control signal is activated, and

the frequency of the second clock signal decreases when the second frequency control signal is activated.