Microchip with faraday cages and internal flexibility sipes

• US 9,568,946 B2
• Filed: 08/07/2014
• Issued: 02/14/2017
• Est. Priority Date: 11/21/2007
• Status: Active Grant

• Current Assignee: Varsgen LLC
• Original Assignee: Varsgen LLC
• Inventors: Ellis, Frampton E.
• Primary Examiner(s): MILAKOVICH, NATHAN J
• Application Number:
  US14/454,282
• Publication Number:
  US 20150055280A1
• Time in Patent Office: 922 Days
• US Class Current: 1/1
• CPC Class Codes: A43B 3/34 with electrical or electronic arrangements
• CPC Class Codes: G06F 1/16 Constructional details or arrangements
• CPC Class Codes: G06F 1/182 with special features, e.g. for use in industrial environments; grounding or shielding against radio frequency interference [RFI] or electromagnetical interference [EMI]
• CPC Class Codes: G06F 1/20 Cooling means
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04L 63/02 for separating internal from external traffic, e.g. firewalls
• CPC Class Codes: H05K 9/0024 Shield cases mounted on a PCB, e.g. cans or caps or conformal shields
• CPC Class Codes: H05K 9/0049 being metallic containers

Abstract

A microchip including an outer chamber, compartment, or bladder; an inner chamber, compartment, or bladder inside said outer chamber, compartment, or bladder; an internal sipe separating at least a part of said inner and outer chambers, compartments, or bladders, and a Faraday cage. The microchip is configured to connect to a network of computers and includes an internal hardware firewall configured to deny access a protected portion of the microchip from the network. The sipe is formed by at least a portion of both an inner surface of the outer chamber, compartment, or bladder and an outer surface of the inner chamber, compartment, or bladder. The surface portions forming the sipe oppose each other and can move relative to each other in a sliding motion. At least a portion of an outer surface of the outer chamber, compartment, or bladder is proximate to an outer surface of the microchip.

Claims

1. A microchip comprising:

at least one outer chamber, compartment, or bladder;

at least one inner chamber, compartment, or bladder inside said outer chamber, compartment, or bladder;

at least one internal sipe separating at least a part of said outer chamber, compartment, or bladder and at least a part of said inner chamber, compartment, or bladder;

at least one Faraday cage; and

said microchip being configured to connect to at least one network of computers, said microchip comprising at least a first internal hardware firewall configured to deny access to at least a first protected portion of said microchip from said network; and

wherein said at least one internal sipe is formed by at least a portion of an inner surface of said outer chamber, compartment, or bladder and at least a portion of an outer surface of said inner chamber, compartment, or bladder; and

the inner and outer surface portions forming said at least one internal sipe oppose each other and can move relative to each other in a sliding motion; and

wherein at least a portion of an outer surface of said outer chamber, compartment, or bladder is proximate to an outer surface of said microchip.

2. The microchip according to claim 1, wherein said at least one outer chamber, compartment, or bladder includes at least one said Faraday Cage.

3. The microchip according to claim 1, wherein said microchip comprises at least one general purpose microprocessor including at least two general purpose core or general purpose processing units, and wherein

at least a first said core or processing unit is located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall;

at least a second said core or processing unit is located within a second portion of said microchip that is not protected by at least said first internal hardware firewall; and

at least said second core or processing unit is separated from said first core or processing unit by at least said first internal hardware firewall and is located between at least said first internal hardware firewall and said at least one network of computers.

4. The microchip according to claim 3, wherein said microchip further comprises a master controller of the microprocessor located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall, and said master controller is configured to control said second said core or processing unit.

5. The microchip according to claim 1, wherein said microchip further comprises a wire cable configured for electronic devices, said wire cable comprising:

at least one wire;

at least one inner layer surrounding a portion of said at least one wire;

at least one outer layer surrounding a portion of said at least one inner layer; and

at least one internal sipe of said wire cable separating at least a part of one said outer layer and at least a part of one said inner layer;

wherein said at least one internal sipe of said wire cable is formed by at least a portion of an inner surface of said outer layer and at least a portion of an outer surface of said inner layer; and

the inner layer and outer layer surface portions of said wire cable forming said at least one internal sipe of said wire cable oppose each other and can move relative to each other in a sliding motion.

6. A microchip comprising:

at least one outer chamber, compartment, or bladder;

at least one inner chamber, compartment, or bladder inside said outer chamber, compartment, or bladder;

at least one internal sipe separating at least a part of said outer chamber, compartment, or bladder and at least a part of said inner chamber, compartment, or bladder;

said microchip being configured to connect to at least one network of computers, said microchip comprising at least four internal hardware firewalls, said at least four internal hardware firewalls configured to deny access to at least four protected portions of said microchip from said network of computers;

at least one Faraday cage; and

wherein said at least one internal sipe is formed by at least a portion of an inner surface of said outer chamber, compartment, or bladder and at least a portion of an outer surface of said inner chamber, compartment, or bladder; and

the inner and outer surface portions forming said at least one internal sipe oppose each other and can move relative to each other in a sliding motion; and

wherein at least a portion of an outer surface of said outer chamber, compartment, or bladder is proximate to an outer surface of said microchip.

7. The microchip according to claim 6, wherein said at least one outer chamber, compartment, or bladder includes at least one said Faraday Cage.

8. The microchip according to claim 6, wherein said microchip comprises at least one general purpose microprocessor including at least two general purpose core or general purpose processing units, and wherein

at least a first said core or processing unit is located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall;

at least a second said core or processing unit is located within a second portion of said microchip that is not protected by at least said first internal hardware firewall; and

at least said second core or processing unit is separated from said first core or processing unit by at least said first internal hardware firewall and is located between at least said first internal hardware firewall and said at least one network of computers.

9. The microchip according to claim 8, wherein said microchip further comprises a master controller of the microprocessor located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall, and said master controller is configured to control said second said core or processing unit.

10. The microchip according to claim 6, wherein said microchip further comprises a wire cable configured for electronic devices, said wire cable comprising:

at least one wire;

at least one inner layer surrounding a portion of said at least one wire;

at least one outer layer surrounding a portion of said at least one inner layer; and

at least one internal sipe of said wire cable separating at least a part of one said outer layer and at least a part of one said inner layer;

wherein said at least one internal sipe of said wire cable is formed by at least a portion of an inner surface of said outer layer and at least a portion of an outer surface of said inner layer; and

the inner layer and outer layer surface portions of said wire cable forming said at least one internal sipe of said wire cable oppose each other and can move relative to each other in a sliding motion.

11. The microchip according to claim 6, wherein said microchip comprises at least one general purpose microprocessor with at least four general purpose cores or general purpose processing units, each protected by at least one of said at least four internal hardware firewalls.

12. A microchip comprising:

at least one outer chamber, compartment, or bladder;

at least one inner chamber, compartment, or bladder inside said outer chamber, compartment, or bladder;

at least one internal sipe separating at least a part of said outer chamber, compartment, or bladder and at least a part of said inner chamber, compartment, or bladder;

at least one Faraday cage; and

said microchip being configured to connect to at least one network of computers, said microchip comprising at least a first internal hardware firewalls configured to deny access to at least a first protected portion of said microchip from said network; and

the microchip further including at least one general purpose microprocessor with at least a general purpose core or processing unit including a master controller of the microprocessor and at least one general purpose core or general purpose processing unit; and

wherein said at least one internal sipe is formed by at least a portion of an inner surface of said outer chamber, compartment, or bladder and at least a portion of an outer surface of said inner chamber, compartment, or bladder; and

the inner and outer surface portions forming said at least one internal sipe oppose each other and can move relative to each other in a sliding motion; and

wherein at least a portion of an outer surface of said outer chamber, compartment, or bladder is proximate to an outer surface of said microchip.

13. The microchip according to claim 12, wherein said at least one outer chamber, compartment, or bladder includes at least one said Faraday Cage.

14. The microchip according to claim 12, wherein said at least one general purpose microprocessor includes at least two general purpose cores or general purpose processing units, and wherein

at least a first said core or processing unit is located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall;

at least a second said core or processing unit is located within a second portion of said microchip that is not protected by at least said first internal hardware firewall; and

at least said second core or processing unit is separated from said first core or processing unit by at least said first internal hardware firewall and is located between at least said first internal hardware firewall and said at least one network of computers.

15. The microchip according to claim 14, wherein said master controller of the microprocessor is located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall, and said master controller is configured to control said second said core or processing unit.

16. The microchip according to claim 12, wherein the master controller of the microprocessor is also protected by a second said internal hardware firewall.

17. The microchip according to claim 12, wherein said microchip further comprises a wire cable configured for electronic devices, said wire cable comprising:

at least one wire;

at least one inner layer surrounding a portion of said at least one wire;

at least one outer layer surrounding a portion of said at least one inner layer; and

at least one internal sipe of said wire cable separating at least a part of one said outer layer and at least a part of one said inner layer;

wherein said at least one internal sipe of said wire cable is formed by at least a portion of an inner surface of said outer layer and at least a portion of an outer surface of said inner layer; and

the inner layer and outer layer surface portions of said wire cable forming said at least one internal sipe of said wire cable oppose each other and can move relative to each other in a sliding motion.