Adaptive flash tuning

• US 9,569,120 B2
• Filed: 08/03/2015
• Issued: 02/14/2017
• Est. Priority Date: 08/04/2014
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Nvmdurance Limited
• Inventors: Sullivan, Joseph, Ryan, Conor Maurice
• Primary Examiner(s): Peugh, Brian
• Application Number:
  US14/816,986
• Publication Number:
  US 20160034206A1
• Time in Patent Office: 561 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 : for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 : Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/349 : Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/36 : Data generation devices, e.g. data inverters
• CPC Class Codes: G11C 29/38 : Response verification devices
• CPC Class Codes: G11C 29/44 : Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/50012 : of timing
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents

Abstract

The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, LUNs and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods).

Claims

1. A flash memory controller that controls the operation of one or more flash memory chips, each chip organized into one or more LUNs, and each LUN associated with one or more blocks of flash memory and one or more control registers storing operating parameters associated with that LUN, the flash memory controller comprising:

(a) an operating parameter database that stores, with respect to each LUN of the one or more flash memory chips, a plurality of sets of operating parameters, each set of operating parameters corresponding to a health stage representing an estimated level of degradation of the flash memory within that LUN;

(b) a controller memory command module that issues read, write and erase controller memory commands to the flash memory chips, wherein each of the flash memory chips implements the controller memory commands by applying varying levels of electrical stimuli to the blocks of flash memory in a LUN in accordance with current values of the operating parameters associated with that LUN; and

(c) an inference engine that;

(i) analyzes a plurality of wear indicators that evidence degradation of the flash memory over time, wherein one of the plurality of wear indicators is a current cumulative number of program/erase cycles performed by the flash memory controller during the operational lifetime of the one or more flash memory chips, and

(ii) determines, based on the analysis of the wear indicators, whether a transition of a LUN from a current health stage to a subsequent health stage is warranted and, if so, replaces the contents of the LUN'"'"'s control registers with the set of operating parameters corresponding to the subsequent health stage.

2. The flash memory controller of claim 1, wherein the plurality of wear indicators includes BER data resulting from the issuance of memory controller commands to read the contents of the flash memory.

3. The flash memory controller of claim 1, wherein the plurality of wear indicators includes timing information with respect to the issuance of one or more controller memory commands.

4. The flash memory controller of claim 1, wherein, with respect to each health stage, the set of operating parameters corresponding to that health stage is the same for each LUN of each of the one or more flash memory chips.

5. The flash memory controller of claim 1, wherein the sets of operating parameters corresponding to the health stages are predetermined in an offline characterization phase prior to the operational lifetime of the one or more flash memory chips.

6. The flash memory controller of claim 1, wherein the inference engine, upon determining that a transition of a LUN from a current health stage to a subsequent health stage is not warranted, employs one or more preventive measures to reduce the rate of degradation of the flash memory over time, and thereby extend the operational lifetime of the one or more flash memory chips.

7. The flash memory controller of claim 6, wherein the preventive measures include one or more of the following:

(a) resting one or more of the blocks of a LUN of the one or more flash memory chips, (b) reducing the usage of one or more blocks of a LUN of the one or more flash memory chips, and (c) moving the data contents of a suspect block to another block in the one or more flash memory chips.

8. A method for controlling the operation of one or more flash memory chips, each chip organized into one or more LUNs, and each LUN associated with one or more blocks of flash memory and one or more control registers storing operating parameters associated with that LUN, the method comprising the following steps:

(a) storing, with respect to each LUN of the one or more flash memory chips, a plurality of sets of operating parameters, each set of operating parameters corresponding to a health stage representing an estimated level of degradation of the flash memory within that LUN;

(b) issuing read, write and erase controller memory commands to the flash memory chips, wherein each of the flash memory chips implements the controller memory commands by applying varying levels of electrical stimuli to the blocks of flash memory in a LUN in accordance with current values of the operating parameters associated with that LUN;

(c) analyzing a plurality of wear indicators that evidence degradation of the flash memory over time, wherein one of the plurality of wear indicators is a current cumulative number of program/erase cycles performed during the operational lifetime of the one or more flash memory chips; and

(d) determining, based on the analysis of the wear indicators, whether a transition of a LUN from a current health stage to a subsequent health stage is warranted and, if so, replacing the contents of the LUN'"'"'s control registers with the set of operating parameters corresponding to the subsequent health stage.

9. The method of claim 8, wherein the plurality of wear indicators includes BER data resulting from the issuance of memory controller commands to read the contents of the flash memory.

10. The method of claim 8, wherein the plurality of wear indicators includes timing information with respect to the issuance of one or more controller memory commands.

11. The method of claim 8, wherein, with respect to each health stage, the set of operating parameters corresponding to that health stage is the same for each LUN of each of the one or more flash memory chips.

12. The method of claim 8, wherein the sets of operating parameters corresponding to the health stages are predetermined in an offline characterization phase prior to the operational lifetime of the one or more flash memory chips.

13. The method of claim 8, further including the step, upon determining that a transition of a LUN from a current health stage to a subsequent health stage is not warranted, of employing one or more preventive measures to reduce the rate of degradation of the flash memory over time, and thereby extend the operational lifetime of the one or more flash memory chips.

14. The method of claim 13, wherein the preventive measures include one or more of the following:

(a) resting one or more of the blocks of a LUN of the one or more flash memory chips, (b) reducing the usage of one or more blocks of a LUN of the one or more flash memory chips, and (c) moving the data contents of a suspect block to another block in the one or more flash memory chips.