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Adaptive flash tuning

  • US 9,569,120 B2
  • Filed: 08/03/2015
  • Issued: 02/14/2017
  • Est. Priority Date: 08/04/2014
  • Status: Active Grant
First Claim
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1. A flash memory controller that controls the operation of one or more flash memory chips, each chip organized into one or more LUNs, and each LUN associated with one or more blocks of flash memory and one or more control registers storing operating parameters associated with that LUN, the flash memory controller comprising:

  • (a) an operating parameter database that stores, with respect to each LUN of the one or more flash memory chips, a plurality of sets of operating parameters, each set of operating parameters corresponding to a health stage representing an estimated level of degradation of the flash memory within that LUN;

    (b) a controller memory command module that issues read, write and erase controller memory commands to the flash memory chips, wherein each of the flash memory chips implements the controller memory commands by applying varying levels of electrical stimuli to the blocks of flash memory in a LUN in accordance with current values of the operating parameters associated with that LUN; and

    (c) an inference engine that;

    (i) analyzes a plurality of wear indicators that evidence degradation of the flash memory over time, wherein one of the plurality of wear indicators is a current cumulative number of program/erase cycles performed by the flash memory controller during the operational lifetime of the one or more flash memory chips, and(ii) determines, based on the analysis of the wear indicators, whether a transition of a LUN from a current health stage to a subsequent health stage is warranted and, if so, replaces the contents of the LUN'"'"'s control registers with the set of operating parameters corresponding to the subsequent health stage.

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