Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control

• US 9,569,186 B2
• Filed: 03/14/2014
• Issued: 02/14/2017
• Est. Priority Date: 10/29/2003
• Status: Active Grant

• Current Assignee: III Holdings 2, LLC (Intellectual Ventures LLC)
• Original Assignee: III Holdings 2, LLC (Intellectual Ventures LLC)
• Inventors: Chheda, Saurabh, Carver, Kristopher, Ashok, Raksit
• Primary Examiner(s): DO, CHAT C
• Assistant Examiner(s): Slachta, Douglas
• Application Number:
  US14/212,737
• Publication Number:
  US 20140372994A1
• Time in Patent Office: 1,068 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 8/4432 Reducing the energy consumption
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method comprising of analyzing and transforming a program executable at compile-time such that a processor design objective is optimized. A method including analyzing an executable to estimate energy consumption of an application component in a processor. A method including transforming an executable to reduce energy consumption in a processor. A processor framework controlled by compiler inserted control that statically exposes parallelism in an instruction sequence. A processor framework to reduce energy consumption in an instruction memory system with compiler inserted control.

Claims

1. A method, comprising:

inputting source files into a source-level compiler to obtain a binary executable;

analyzing a representation of the binary executable to identify information relating to micro-operations of components of a microprocessor;

responsive to analyzing the representation of the binary executable to identify the information relating to the micro-operations of the components of the microprocessor, generating control information comprising instructions that contain data that renders unnecessary at least one of the micro-operations;

transforming the representation of the binary executable obtained from the source-level compiler into a binary executable that is different than the binary executable obtained from the source-level compiler, the transformation including combining the generated control information with at least one of instructions of the representation of the binary executable; and

predicting inactive periods of resources in the microprocessor using static information produced through a compilation of a computer program;

wherein the control information is configured to;

control the resources during the inactive periods so as to reduce energy consumption of the resources during the inactive periods;

reduce an amount of voltage supplied to the resources during the inactive periods relative to an amount of voltage supplied to the resources during active periods of the resources; and

precharge a cache of the resources to reduce leakage in bitlines associated with the cache.

2. The method of claim 1, wherein transforming the representation of the binary executable comprises removing a branched instruction from the instructions of the representation of the binary executable.

3. The method of claim 1, further comprising:

generating the representation of the binary executable by replacing a first instruction sequence corresponding to the binary executable obtained from the source-level compiler with a second instruction sequence that is different than the first instruction sequence.

4. The method of claim 3, wherein the representation of the binary executable comprises program blocks, wherein analyzing the representation of the binary executable comprises identifying a subset of the program blocks associated with a specific criticality, and the method further comprises:

generating the second instruction sequence responsive to identifying the subset of the program blocks associated with the specific criticality.

5. The method of claim 1, wherein transforming the representation of the binary executable further comprises rearranging the instructions of the representation of the binary executable.

6. The method of claim 5, wherein rearranging the instructions of the representation of the binary executable obtained from the source-level compiler further comprises reordering the instructions of the representation of the binary executable obtained from the source-level compiler to increase an amount of parallel instructions.

7. The method of claim 1, wherein analyzing the representation of the binary executable comprises identifying instructions that may be executed in parallel, and wherein the control information identifies instructions in the binary executable obtained responsive to the transformation that may be executed in parallel.

8. The method of claim 7, wherein the control information comprises a control bit preceding the instructions in the binary executable obtained responsive to the transformation that may be executed in parallel.

9. The method of claim 7, wherein identifying instructions that may be executed in parallel further comprises identifying parallel instructions in blocks of instructions associated with the binary executable obtained from the source-level compiler.

10. The method of claim 7, wherein identifying instructions that may be executed in parallel further comprises exposing parallel instructions in critical loops in the binary executable obtained from the source-level compiler.

11. The method of claim 7, wherein the control information comprises data to be removed from an instruction sequence of the binary executable obtained responsive to the transformation before a corresponding portion of the instruction sequence enters a pipeline of the microprocessor.

12. The method of claim 7, wherein the control information is usable during executing of the binary executable obtained responsive to the transformation to improve operation of the microprocessor relative to execution of the binary executable obtained from the source-level compiler.

13. The method of claim 12, wherein the control information is usable to reduce energy consumption of the microprocessor during execution of the binary executable obtained responsive to the transformation.

14. A memory device having instructions stored thereon that, in response to execution by a processing device, cause the processing device to perform operations comprising:

analyzing a representation of a first binary executable to identify information relating to micro-operations of components of a microprocessor;

responsive to analyzing the representation of the first binary executable to identify the information relating to the micro-operations of the components of the microprocessor, generating control information comprising instructions that contain data that renders unnecessary at least one of the micro-operations;

transforming the representation of the first binary executable into a second binary executable that is different than the first binary executable, the transformation including combining the generated control information with at least one of instructions of the representation of the first binary executable; and

predicting inactive periods of resources in the microprocessor using static information produced through a compilation of a computer program;

wherein the control information is configured to;

control the resources during the inactive periods so as to reduce energy consumption of the resources during the inactive periods;

reduce an amount of voltage supplied to the resources during the inactive periods relative to an amount of voltage supplied to the resources during active periods of the resources; and

precharge a cache of the resources to reduce leakage in bitlines associated with the cache.

15. The memory device of claim 14, wherein transforming the representation of the first binary executable further comprises rearranging the instructions of the representation of the first binary executable.

16. The memory device of claim 14, wherein transforming the representation of the first binary executable comprises removing a branched instruction from the instructions of the representation of the first binary executable.

17. The memory device of claim 14, wherein the cache comprises first and second memory structures, the first memory structure being smaller than the second memory structure;

and

wherein precharging is to be performed on the second memory structure but not on the first memory structure.

18. The memory device of claim 14, wherein the cache comprises first and second memory structures, the first memory structure being smaller than the second memory structure;

wherein the static information identifies instructions in the computer program, the instructions in the computer program having instruction footprints that can be accommodated by the first memory structure;

wherein the first memory structure is used for the instructions in the computer program; and

wherein the control information is configured to reduce voltage to the second memory structure during execution of the instructions in the computer program.

19. The memory device of claim 14, wherein the operations further comprise generating the representation of the first binary executable by replacing a first instruction sequence corresponding to the first binary executable with a second instruction sequence that is different than the first instruction sequence.

20. The memory device of claim 19, wherein the representation of the binary first executable comprises program blocks, wherein analyzing the representation of the first binary executable comprises identifying a subset of the program blocks associated with a specific criticality, and the operations further comprise:

generating the second instruction sequence responsive to identifying the subset of the program blocks associated with the specific criticality.