Decomposing operations in more than one dimension into one dimensional point operations

• US 9,569,218 B2
• Filed: 12/30/2011
• Issued: 02/14/2017
• Est. Priority Date: 12/30/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Krig, Scott A.
• Primary Examiner(s): Tseng, Cheng-Yuan
• Application Number:
  US13/992,279
• Publication Number:
  US 20130297908A1
• Time in Patent Office: 1,873 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

A processing architecture uses stationary operands and opcodes common on a plurality of processors. Only data moves through the processors. The same opcode and operand is used by each processor assigned to operate, for example, on one row of pixels, one row of numbers, or one row of points in space.

Claims

1. A method comprising:

converting processor-based operations in more than one dimension into a series of one dimensional operations;

programming a plurality of parallel processors with the same operand and the same opcode;

performing a plurality of parallel operations using each of said processors and said operand to generate results and storing the results from each processor in one line in a memory;

providing only one parallel processor for each row of pixels in a frame; and

providing two processors, one to process words of a first size and the other to process words of a second size.

2. The method of claim 1 including converting an area operation into a series of one dimensional operations.

3. The method of claim 2 including converting an area operation into point operations implemented by memory writes into memory cells.

4. The method of claim 3 including combining a value of a first memory cell of said memory cells with an operand according to a processing opcode and accumulating results back into the first memory cell.

5. The method of claim 1 including performing a precision and numeric conversion in said processors.

6. The method of claim 1 wherein moving only data, and not instructions, along a processing pipeline.

7. The method of claim 1 including providing a storage and accumulation cell in said memory for each pixel.

8. The method of claim 7 including enabling each processor to perform both a point operation and an accumulation into the storage cell.

18. The method of claim 1 including providing a processor for each memory cell in a two dimensional array of memory cells.

9. A non-transitory computer readable medium storing instructions to implement a method comprising:

converting operations in more than one dimension into a series of one dimensional operations;

programming a plurality of parallel processors with the same operand and the same opcode;

performing a plurality of parallel operations using each of said processors and said operand to generate results and storing the results from each processor in one line in a memory;

providing only one parallel processor for each row of pixels in a frame; and

providing two processors, one to process words of a first size and the other to process words of a second size.

10. The medium of claim 9 including converting an area operation into a series of one dimensional operations.

11. The medium of claim 10 including converting an area operation into point operations implemented by memory writes into memory cells.

12. The medium of claim 11 including combining a value of a first memory cell value of said memory cells with an operand according to a processing opcode and accumulating results back into the first memory cell.

13. An apparatus comprising:

a plurality of parallel processors, including only one parallel processor for each row of pixels in a frame;

a processor to convert operations in more than one dimension into a series of one dimensional operations, to program a plurality of parallel processors with the same operand and the same opcode, and to perform a plurality of parallel operations using each of said processors and said operand to generate results and storing the results from each processor in one line in a memory, and convert an area operation into a series of one dimensional operations; and

a storage coupled to said processor.

14. The apparatus of claim 13, said processor to convert area operations into a series of one dimensional operations.

15. The apparatus of claim 14, said processor to convert an area operation into point operations implemented by memory writes into memory cells.

16. The apparatus of claim 15, said processor to combine a value of a first memory cell of said memory cells with an operand according to a processing opcode and accumulating results back into the first memory cell.

17. The apparatus of claim 13 including a plurality of parallel processors programmed with the same operand and the same opcode, said processors to perform a plurality of parallel operations using each of said processors and said operand to generate results and store the results from each processor in one line in a memory.

19. A method comprising:

converting processor-based operations in more than one dimension into a series of one dimensional operations;

programming a plurality of parallel processors with the same operand and the same opcode;

performing a plurality of parallel operations using each of said processors and said operand to generate results and storing the results from each processor in one line in a memory;

providing only one parallel processor for each row of pixels in a frame; and

providing a two-dimensional array of processors, one for each pixel in an image to be processed.

20. A method comprising:

converting processor-based operations in more than one dimension into a series of one dimensional operations;

programming a plurality of parallel processors with the same operand and the same opcode;

performing a plurality of parallel operations using each of said processors and said operand to generate results and storing the results from each processor in one line in a memory;

providing only one parallel processor for each row of pixels in a frame; and

providing a processor for each memory cell in a two dimensional array of memory cells.