Storing corresponding data units in a common storage unit
First Claim
1. A method comprising:
- receiving, by a storage device, a plurality of logical blocks to be stored in the storage device, wherein a first set of addresses comprises logical block addresses (LBAs) of the plurality of logical blocks;
determining an intersection of the first set of addresses with a second set of addresses, wherein the second set of addresses comprises LBAs of logical blocks in a storage unit of the storage device;
comparing the size of the determined intersection with a threshold size; and
storing each of the logical blocks having LBAs in the determined intersection of addresses in a common storage unit of the storage device, wherein the common storage unit is separate from the storage unit in which the logical blocks corresponding to the second set of addresses are stored when the size of the determined intersection is equal to or greater than the threshold size.
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Accused Products
Abstract
A storage device controller may segregate data units that are typically accessed together to a common storage unit. In one example, a storage device includes a control unit configured to receive a plurality of logical blocks to be stored in the storage device, wherein a first set of addresses comprises logical block addresses (LBAs) of the plurality of logical blocks, and a non-volatile memory configured to store logical blocks in a plurality of storage units, wherein one of the plurality of storage units includes logical blocks corresponding to a second set of addresses. The control unit may determine an intersection of the first set of addresses with the second set of addresses and to store each of the logical blocks having LBAs in the determined intersection of addresses in a common storage unit of the storage device, wherein the common storage unit comprises one of the plurality of storage units.
20 Citations
23 Claims
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1. A method comprising:
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receiving, by a storage device, a plurality of logical blocks to be stored in the storage device, wherein a first set of addresses comprises logical block addresses (LBAs) of the plurality of logical blocks; determining an intersection of the first set of addresses with a second set of addresses, wherein the second set of addresses comprises LBAs of logical blocks in a storage unit of the storage device; comparing the size of the determined intersection with a threshold size; and storing each of the logical blocks having LBAs in the determined intersection of addresses in a common storage unit of the storage device, wherein the common storage unit is separate from the storage unit in which the logical blocks corresponding to the second set of addresses are stored when the size of the determined intersection is equal to or greater than the threshold size. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A storage device comprising:
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a control unit configured to receive a plurality of logical blocks to be stored in the storage device, wherein a first set of addresses comprises logical block addresses (LBAs) of the plurality of logical blocks; and a non-volatile memory configured to store logical blocks in a plurality of storage units, wherein one of the plurality of storage units includes logical blocks corresponding to a second set of addresses, wherein the control unit is configured to determine an intersection of the first set of addresses with the second set of addresses, to compare the size of the determined intersection with a threshold size, and to store each of the logical blocks having LBAs in the determined intersection of addresses in a common storage unit of the storage device, wherein the common storage unit comprises one of the plurality of storage units and is separate from the one of the plurality of storage units including the logical blocks corresponding to the second set of addresses when the size of the determined intersection is equal to or greater than the threshold size. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A computer-readable storage medium encoded with instructions that cause a processor to:
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receive a plurality of logical blocks to be stored in a storage device, wherein a first set of addresses comprises logical block addresses (LBAs) of the plurality of logical blocks; determine an intersection of the first set of addresses with a second set of addresses, wherein the second set of addresses comprises LBAs of logical blocks in a storage unit of the storage device; compare the size of the determined intersection with a threshold size; and store each of the logical blocks having LBAs in the determined intersection of addresses in a common storage unit of the storage device, wherein the common storage unit is separate from the one of the plurality of storage units including the logical blocks corresponding to the second set of addresses when the size of the determined intersection is equal to or greater than the threshold size. - View Dependent Claims (19, 20, 21, 22, 23)
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Specification