Method and device for processing video image

• US 9,570,036 B2
• Filed: 05/22/2013
• Issued: 02/14/2017
• Est. Priority Date: 10/18/2012
• Status: Active Grant

• Current Assignee: Leyard Optoelectronic Co., Ltd.
• Original Assignee: Leyard Optoelectronic Co., Ltd.
• Inventors: Lei, Weilin, Lu, Changjun
• Primary Examiner(s): YENKE, BRIAN P
• Application Number:
  US14/436,759
• Publication Number:
  US 20150294640A1
• Time in Patent Office: 1,364 Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2340/04 Changes in size, position or resolution of an image
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 2340/0442 Handling or displaying different aspect ratios, or changing the aspect ratio
• CPC Class Codes: G09G 3/2096 Details of the interface to the display terminal specific for a flat panel suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 5/00 Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators image data processing or generation, in general G06T
• CPC Class Codes: G09G 5/005 Adapting incoming signals to the display format of the display terminal
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: H04N 21/234309 by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4 or from Quicktime to Realvideo conversion of standards in analog television systems H04N7/01
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/440263 by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 5/14 Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 7/0122 the input and the output signals having different aspect ratios

Abstract

A method and device for processing a video image are provided. The method comprises: receiving an original video image; adjusting a signal clock frequency of the original video image to acquire a processed video image; after a command signal input by a user is received, capturing the processed video image according to a preset size to acquire a video image corresponding to a display window of the preset size; and encoding the video image corresponding to the display window of the preset size to acquire an encoded video image. According to the method and device for processing the video image disclosed by the disclosure, new line, field and blanking synchronization signals are acquired through adjusting the clock frequency of an input image, and then, the corresponding capturing operation and outputting operation are performed according to the image display requirements of the user, so that the effect that video images with any resolution are reliably and stably displayed in the best display area range is realized.

Claims

1. A method for processing a video image, comprising:

receiving an original video image;

adjusting a signal clock frequency of the original video image to acquire a processed video image;

after a command signal input by a user is received, capturing the processed video image according to a preset size to acquire a video image corresponding to a display window of the preset size; and

encoding the video image corresponding to the display window of the preset size to acquire an encoded video image,

wherein the command signal comprises a preset abscissa and a preset ordinate, wherein after the command signal input by the user is received, the step of capturing the processed video image according to the preset size to acquire the video image corresponding to the display window of the preset size comprises;

performing a pixel point computation according to a first formula to acquire the maximum number Ho of horizontal pixel points of the display window of the preset size, wherein the first formula is;

2. The method according to claim 1, wherein the step of adjusting the signal clock frequency of the original video image to acquire the processed video image comprises:

extracting an original line signal, an original field signal, an original blanking signal and an original blanking masking signal from a control signal of the original video image;

performing reset count for the original field signal at jump points of the original field signal by taking the original line signal as a clock to acquire a field synchronization signal;

performing reset count for the original line signal at jump points of the original line signal by taking a fixed pixel clock frequency as a clock to acquire a line synchronization signal;

performing reset count for the original blanking signal at jump points which are moments greater than a synchronization head of the line synchronization signal by taking the line synchronization signal as a clock to acquire a blanking synchronization signal;

performing reset count for the original blanking masking signal at jump points of the blanking synchronization signal by taking the blanking synchronization signal as a clock to acquire a blanking masking signal; and

generating a processed video control signal according to the field synchronization signal, the line synchronization signal, the blanking synchronization signal and the blanking masking signal, and acquiring the processed video image.

3. The method according to claim 1, wherein, after receiving the original video image, the method further comprises:

receiving the command signal input by the user and parsing the command signal to acquire the preset abscissa and the preset ordinate.

4. The method according to claim 1, wherein, before adjusting the signal clock frequency of the original video image to acquire the processed video image, the method further comprises:

detecting whether a data signal of the original video image is a DDR signal; and

in a case where the data signal of the original video image is the DDR signal, adjusting a bit width of the data signal of the original video image to acquire an original video image of a clock single-edge transmission mode.

5. The method according to claim 1, wherein, after adjusting the signal clock frequency of the original video image to acquire the processed video image, the method further comprises:

performing a Ping-Pong access operation for the processed video image by taking the clock frequency of the original video image as a storing clock and taking a blanking signal of the processed video image as a storing enable signal.

6. A device for processing a video image, comprising:

a receiving module receiving an original video image;

a first processing module adjusting a signal clock frequency of the original video image to acquire a processed video image;

a second processing module, after a command signal input by a user is received, capturing the processed video image according to a preset size to acquire a video image corresponding to a display window of the preset size; and

an encoding module encoding the video image corresponding to the display window of the preset size to acquire an encoded video image,

wherein the command signal comprises a preset abscissa and a preset ordinate, wherein the second processing module comprises;

a first computation module, performing pixel point computation according to a first formula to acquire the maximum number Ho of horizontal pixel points of the display window of the preset size, wherein the first formula is;

7. The device according to claim 6, wherein the first processing module comprises:

an extracting module extracting an original line signal, an original field signal, an original blanking signal and an original blanking masking signal from a control signal of the original video image;

a first counting module performing reset count for the original field signal at jump points of the original field signal by taking the original line signal as a clock to acquire a field synchronization signal;

a second counting module performing reset count for the original line signal at jump points of the original line signal by taking a fixed pixel clock frequency as a clock to acquire a line synchronization signal;

a third counting module performing reset count for the original blanking signal at jump points which are moments greater than a synchronization head of the line synchronization signal, by taking the line synchronization signal as a clock to acquire a blanking synchronization signal;

a fourth counting module performing reset count for the original blanking masking signal at jump points of the blanking synchronization signal by taking the blanking synchronization signal as a clock to acquire a blanking masking signal; and

a fourth sub-processing module generating a control signal of the processed video image according to the field synchronization signal, the line synchronization signal, the blanking synchronization signal and the blanking masking signal, and acquire the processed video image.

8. The device according to claim 6, wherein, after the receiving module receives the original video image, the device further comprises:

a third processing module receiving the command signal input by the user and parse the command signal to acquire the preset abscissa and the preset ordinate.

9. The device according to claim 6, wherein, before the first processing module adjusts the signal clock frequency of the original video image to acquire the processed video image, the device further comprises:

a detecting module detecting whether a data signal of the original video image is a DDR signal; and

a fourth processing module, in a case where the data signal of the original video image is the DDR signal, adjusting a bit width of the data signal of the original video image to acquire an original video image signal of a clock single-edge transmission mode.

10. The device according to claim 6, wherein, after the first processing module adjusts the signal clock frequency of the original video image to acquire the processed video image, the device further comprises:

a reading module performing a Ping-Pong access operation for the processed video image by taking the clock frequency of the original video image as a storing clock and taking the blanking signal of the processed video image as a storing enable signal.