Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes

• US 9,570,118 B2
• Filed: 12/02/2015
• Issued: 02/14/2017
• Est. Priority Date: 09/09/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Lee, Winston, Kim, Ha Soo
• Primary Examiner(s): King, Douglas
• Application Number:
  US14/957,029
• Publication Number:
  US 20160086638A1
• Time in Patent Office: 440 Days
• Field of Search: 365/226, 365/227, 365/229, 365/230.06
• US Class Current: 1/1
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail.

Claims

1. A memory, comprising:

peripheral circuitry powered by a first voltage provided by a variable first power supply;

a memory array powered by a second voltage provided by a variable second power supply;

a switch connected between the peripheral circuitry and the memory array;

control circuitry configured to close the switch when the first and second voltages are the same and to open the switch when the first and second voltages are not the same; and

voltage translation circuitry configured to shift a voltage level of an address signal output by the peripheral circuitry, from the first voltage to the second voltage for input of the signal by the memory array;

wherein the memory is configured to enter a leakage reduction mode in which the voltage translation circuitry is disconnected from power and the second voltage is reduced to reduce current leakage from the memory array to the peripheral circuitry.

2. The memory of claim 1, wherein the second power supply is configured to reduce the second voltage during the leakage reduction mode.

3. The memory of claim 1, wherein the address signal is received by the voltage translation circuitry from an address decoder in the peripheral circuitry.

4. The memory of claim 1, wherein the voltage translation circuitry is configured to bias the second voltage by grounding a voltage terminal of the peripheral circuitry supplying the first voltage.

5. The memory of claim 1, wherein the voltage translation circuitry is configured to bias the second voltage by reducing the second voltage to a minimum data retention voltage for the memory array.

6. The memory of claim 1, wherein the voltage translation circuitry is configured to bias the second voltage by coupling a bias voltage source to a memory array ground plane.

7. The memory of claim 1, wherein the voltage translation circuitry is configured to bias the second voltage by coupling a diode to a memory array ground plane, wherein the diode is configured to raise a voltage level of the memory array ground plane by a threshold voltage of the diode.

8. The memory of claim 1, wherein the second voltage is greater than the first voltage.

16. The memory of claim 1, further comprising:

a power supply output configured to power the memory array; and

a first switch connected between the power supply output and the peripheral circuitry to provide the first voltage to the peripheral circuitry.

9. A method for reducing power consumption in a memory, comprising:

powering peripheral circuitry at a first voltage provided by a variable first power supply;

powering a memory array at a second voltage provided by a variable second power supply;

closing a switch connected between the peripheral circuitry and the memory array when the first and second voltages are the same;

opening the switch when the first and second voltages are not the same;

shifting, by a translation circuit, a voltage level of an address signal, that is output by the peripheral circuitry, from the first voltage to the second voltage for input of the signal to the memory array; and

entering a leakage reduction mode by disconnecting power from the translation circuit and by reducing the second voltage to reduce current leakage from the memory array to the peripheral circuitry.

10. The method of claim 9, further comprising:

disconnecting the peripheral circuitry from a source of the first voltage in the leakage reduction mode.

11. The method of claim 9, wherein the second voltage is biased by grounding a voltage terminal of the peripheral circuitry supplying the first voltage.

12. The method of claim 9, wherein the second voltage is biased by reducing the second voltage to a minimum data retention voltage for the memory array.

13. The method of claim 9, wherein the second voltage is biased by coupling a bias voltage source to a memory array ground plane.

14. The method of claim 9, wherein the second voltage is biased by coupling a diode to a memory array ground plane, wherein the diode is configured to raise a voltage level of the memory array ground plane by a threshold voltage of the diode.

15. The method of claim 9, wherein the second voltage is greater than the first voltage.