Method of operating incrementally programmable non-volatile memory

• US 9,570,161 B2
• Filed: 04/18/2016
• Issued: 02/14/2017
• Est. Priority Date: 08/05/2013
• Status: Active Grant

• Current Assignee: Jonker LLC
• Original Assignee: Jonker LLC
• Inventors: Liu, David K. Y.
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/131,524
• Publication Number:
  US 20160307624A1
• Time in Patent Office: 302 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a V_t representing a particular binary logic state is changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.

Claims

1. A method of erasing or resetting an array of non-volatile memory cells on an integrated circuit where each of such cells in the array is adapted to store data through injection of hot carriers into a floating gate, the method comprising:

a) for each program cycle in which said array is configured with a new data pattern;

i. providing an original target highest threshold voltage for programming the cells in said program cycle, and

ii. programming cells in said array selectively to store said new data pattern during said program cycle through injected electrons; and

b) performing a reset of the array prior to programming said cells in said array in a subsequent program cycle, further injecting electrons to all of the memory cells, such that the threshold voltage of every cell in the array is substantially same as the original highest threshold voltage used in a prior program cycle;

wherein said cells in said array are operated as one-time programmable (OTP) and/or multi-time programmable (MTP) cells.

2. The method of claim 1, further including a step:

operating a second array on the integrated circuit with a second different original target highest threshold voltage during each program cycle.

3. The method of claim 2, wherein cells in said array are configured as single bit cells, and cells in said second array are configured as multi-bit cells.

4. The method of claim 1, wherein otherwise nominal OTP cells operate as MTP cells by virtue of altering program threshold levels representing a particular logic state during different program cycles.

5. The method of claim 1, wherein a reference cell used for read operations is changed after each program cycle.

6. The method of claim 1, further including a step:

performing said subsequent program cycle automatically in response to a passage of time.

7. The method of claim 1 further including a step:

performing said subsequent program cycle automatically in response to detecting degradation of cells in said array.

8. The method of claim 1 wherein erasing of cells is performed without removing charge.

9. A method of programming an array of non-volatile memory cells on an integrated circuit where each of such cells in the array is adapted to store data through injection of hot carriers into a floating gate, the method comprising:

a) for each program cycle in which said array is configured with a first data pattern;

i. providing a first target threshold voltage for programming the cells in said program cycle, and

ii. programming cells in said array selectively to store said first data pattern during said program cycle through injected electrons;

b) resetting the array by injecting electrons to all the array cells, such that the threshold voltage of every cell in the array is substantially the same as the first target threshold voltage used in an immediately prior program cycle; and

c) programming cells in said array selectively to store a second data pattern during a second program cycle using injected electrons to establish a second target threshold voltage that is higher than said first target threshold voltage;

wherein otherwise nominal OTP cells are transformed into few-time or multi-time cells by altering their initial threshold levels at each programming cycle representing a particular logic state.