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Nonvolatile memory device with reduced coupling noise and driving method thereof

  • US 9,570,168 B2
  • Filed: 08/21/2015
  • Issued: 02/14/2017
  • Est. Priority Date: 08/22/2014
  • Status: Active Grant
First Claim
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1. A nonvolatile memory device comprising:

  • a plurality of memory banks;

    a read global bit line shared by the plurality of memory banks;

    a write global bit line, separate from the read global bit line, shared by the plurality of memory banks;

    a read circuit connected with the read global bit line and configured to perform a read operation; and

    a discharge control circuit connected with the write global bit line and configured to primarily discharge a charge of the write global bit line during an initialization interval after a power-up operation.

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