Nonvolatile memory device with reduced coupling noise and driving method thereof

• US 9,570,168 B2
• Filed: 08/21/2015
• Issued: 02/14/2017
• Est. Priority Date: 08/22/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jae-Yun, Sun, Woo-Jung, Lee, Kwang-Jin, Jeong, Dong-Hoon, Cho, Beak-Hyung
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US14/832,229
• Publication Number:
  US 20160055905A1
• Time in Patent Office: 543 Days
• Field of Search: 365/148, 365/158, 365/189.16, 365/222, 365/230.03, 365/189.07, 365/189.08, 365/63, 365/189.15, 365/185.13
• US Class Current: 1/1
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2207/2209 Concurrent read and write
• CPC Class Codes: G11C 2207/2281 Timing of a read operation
• CPC Class Codes: G11C 2207/229 Timing of a write operation
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.

Claims

1. A nonvolatile memory device comprising:

a plurality of memory banks;

a read global bit line shared by the plurality of memory banks;

a write global bit line, separate from the read global bit line, shared by the plurality of memory banks;

a read circuit connected with the read global bit line and configured to perform a read operation; and

a discharge control circuit connected with the write global bit line and configured to primarily discharge a charge of the write global bit line during an initialization interval after a power-up operation.

2. The nonvolatile memory device of claim 1, wherein the discharge control circuit is configured to primarily discharge the write global bit line before a write command is input.

3. The nonvolatile memory device of claim 1, wherein the read operation is a read while write (RWW) operation such that the read circuit is configured to perform the read operation while a write operation is being performed.

4. The nonvolatile memory device of claim 1, wherein the discharge control circuit is configured to secondarily discharge the write global bit line after a write command is input, said secondarily discharging not overlapping a develop interval of the read operation.

5. The nonvolatile memory device of claim 4, wherein the discharge control circuit is configured to not secondarily discharge the write global bit line while a protection signal is enabled, and

the protection signal is enabled during a protection interval corresponding to the develop interval of the read operation.

6. The nonvolatile memory device of claim 1, wherein the discharge control circuit is configured to secondarily discharge the write global bit line at a predetermined cycle.

7. The nonvolatile memory device of claim 6, wherein the predetermined cycle is measured by a timer.

8. The nonvolatile memory device of claim 1, further comprising a monitoring circuit configured to sense a voltage level of the write global bit line,

wherein the discharge control circuit is configured to secondarily discharge the write global bit line when the voltage level of the write global bit line is determined to abnormally increase, based on a sensing result of the monitoring circuit.

9. The nonvolatile memory device of claim 1, wherein the discharge control circuit is configured to secondarily discharge the write global bit line whenever a preactive command of the read operation is input, the preactive command being a command that is input together with an upper address of the read operation.

10. The nonvolatile memory device of claim 9, wherein the discharge control circuit is configured to not discharge the write global bit line when an active command of the read operation is input, the active command being a command that is input together with a lower address of the read operation.

11. The nonvolatile memory device of claim 1, wherein each of the plurality of memory banks includes a plurality of nonvolatile memory cells using resistors.

12. A nonvolatile memory device comprising:

a plurality of memory banks;

a plurality of read global bit lines shared by the plurality of memory banks;

a plurality of write global bit lines shared by the plurality of memory banks, wherein each read global bit line of the plurality of read global bit lines and write global bit line of the plurality of write global bit lines that share a corresponding one of the plurality of memory banks are separate from one another;

a read circuit connected with the plurality of read global bit lines and configured to read data from memory cells in the plurality of memory banks through the plurality of read global bit lines;

a discharge control circuit connected with the plurality of write global bit lines and configured to cyclically discharge charges of the plurality of write global bit lines;

a column selection circuit configured to select one among the plurality of write global bit lines in response to a write global column selection signal and configured to select one among the plurality of read global bit lines in response to a read global selection signal;

a write circuit connected with the plurality of write global bit lines and configured to write data to the memory cells in the plurality of memory banks through the plurality of write global bit lines; and

a controller configured to control the read circuit, the discharge control circuit, the column selection circuit and the write circuit.

13. The nonvolatile memory device of claim 12, wherein the read circuit is configured to perform a read while write (RWW) operation such that the read circuit is configured to perform the read operation while the write circuit is performing a write operation.

14. The nonvolatile memory device of claim 13, wherein the discharge control circuit is configured to not cyclically discharge the plurality of write global bit lines during a develop interval of the RWW operation.

15. The nonvolatile memory device of claim 14, wherein the discharge control circuit is configured to not cyclically discharge the plurality of write global bit lines while a protection signal is enabled, and

the protection signal is enabled during a protection interval corresponding to the develop interval of the RWW operation.

16. The nonvolatile memory device of claim 12, wherein the discharge control circuit is configured to not cyclically discharge the plurality of write global bit lines during a program interval of a write operation.

17. The nonvolatile memory device of claim 12, wherein electric charges are cyclically removed in the plurality of write global bit lines in a floating state when the plurality of write global bit lines are cyclically discharged.

18. A memory card comprising:

a card controller configured to control an operation of the memory card; and

a nonvolatile memory coupled to the card controller,

wherein the nonvolatile memory includes;

a plurality of memory banks;

a plurality of read global bit lines shared by the plurality of memory banks;

a plurality of write global bit lines shared by the plurality of memory banks, wherein each read global bit line of the plurality of read global bit lines and write global bit line of the plurality of write global bit lines that share a corresponding one of the plurality of memory banks are separate from one another;

a read circuit connected with the plurality of read global bit lines and configured to read data from memory cells in the plurality of memory banks through the plurality of read global bit lines;

a discharge control circuit connected with the plurality of write global bit lines, the discharge control circuit being configured either to cyclically discharge charges of the plurality of write global bit lines or to discharge charges of the plurality of write global bit lines during an initialization interval after a power-up operation;

a write circuit connected with the plurality of write global bit lines and configured to write data to the memory cells in the plurality of memory banks through the plurality of write global bit lines; and

a memory controller configured to control the read circuit, the discharge control circuit, and the write circuit.

19. The memory card of claim 18, wherein the discharge control circuit is configured to secondarily discharge the plurality of write global bit lines after a write command is input, said secondarily discharging not overlapping a develop interval of the read Operation.

20. The memory card of claim 18, wherein the plurality of write global bit lines are discharged during the initialization interval after the power-up operation and are cyclically discharged thereafter.