Incrementally programmable non-volatile memory
First Claim
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1. A programmable non-volatile device having at least a first programmed state and a second unprogrammed state which can be varied in time and comprising:
- a programming control circuit configured to generate a programming voltage;
a control gate configured to apply said programming voltage from said programming control circuit to the device;
wherein said programming voltage includes at least a first voltage value and a second higher voltage value;
a floating gate coupled to the control gate and adapted to store a first charge amount corresponding to said first programmed state in response to said programming voltage including said first voltage value being applied at a first programming time;
said floating gate being further adapted to store a second charge amount that also corresponds to said first programmed state in response to said programming voltage including said second voltage value being applied at a second programming time;
wherein said programming control circuit is further configured to perform a reset operation which sets said floating gate to a reference state in which at least said first charge amount is stored on said floating gate prior to setting such gate to store said second charge amount at said second programming time;
further wherein the device does not include an electrical based erase circuit which removes electric charge from said floating gate for erase operations and is adapted to store a first unique binary programmed state (1 or
0) at different times using both a first threshold value and a second separate threshold value set for the device.
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Abstract
An array of programmable non-volatile devices, such as a nominal OTP cell, is adapted such that a Vt representing a particular binary logic state can be changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.
42 Citations
24 Claims
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1. A programmable non-volatile device having at least a first programmed state and a second unprogrammed state which can be varied in time and comprising:
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a programming control circuit configured to generate a programming voltage; a control gate configured to apply said programming voltage from said programming control circuit to the device; wherein said programming voltage includes at least a first voltage value and a second higher voltage value; a floating gate coupled to the control gate and adapted to store a first charge amount corresponding to said first programmed state in response to said programming voltage including said first voltage value being applied at a first programming time; said floating gate being further adapted to store a second charge amount that also corresponds to said first programmed state in response to said programming voltage including said second voltage value being applied at a second programming time; wherein said programming control circuit is further configured to perform a reset operation which sets said floating gate to a reference state in which at least said first charge amount is stored on said floating gate prior to setting such gate to store said second charge amount at said second programming time; further wherein the device does not include an electrical based erase circuit which removes electric charge from said floating gate for erase operations and is adapted to store a first unique binary programmed state (1 or
0) at different times using both a first threshold value and a second separate threshold value set for the device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. In a programmable non-volatile memory device including a programming circuit, an array of cells each having a floating gate, a control gate, a source region, a drain region, and a channel coupling said source region and said drain region, the improvement comprising:
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the memory device being adapted such that said array of cells is initialized at a first state, and a) can be set by the programming circuit to a second single binary logic state (1 or
0) at a first threshold voltage (Vt1) in response to a first program operation; andb) can be set by the programming circuit to said same second single binary logic state (1 or
0) at a second different threshold voltage (Vt2) which is higher than Vt1 in response to a second program operation; andsaid programming control circuit is further configured to perform a reset operation which sets each cell in said array to a reference state threshold voltage (Vr) equal at least to a prior programming state threshold voltage prior to setting such cell to a new state at said second programming time; wherein the memory device does not require an electrical based erase controller to remove electric charge from each floating gate of such array of cells between program operations. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. In a programmable non-volatile device including a programming control circuit, an array of cells each having a floating gate, a control gate, a source region, a drain region, and a channel coupling said source region and said drain region, the improvement comprising:
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the device being adapted such that; a first portion of the array of cells can be set to a first initial state Vt, and can be programmed to a second single binary logic state (1 or
0) at a first threshold voltage (Vt1) higher than Vt;a second portion of the array of cells can be set to a second initial state which is also higher than Vt, and can be programmed to said same second single binary logic state (1 or 0 ) as programmed in said first portion at a second threshold voltage (Vt2) which is higher than Vt1; and the programming control circuit is configured to perform a reset operation which can set each cell in a respective portion of the array to a reference state equal to a prior programming state threshold voltage (Vt1 or Vt2) before programming such cell to a new threshold voltage. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification