Use of an external getter to reduce package pressure

• US 9,570,321 B1
• Filed: 10/20/2015
• Issued: 02/14/2017
• Est. Priority Date: 10/20/2015
• Status: Active Grant

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Black, Stephen H., Kennedy, Adam M.
• Primary Examiner(s): Potter, Roy
• Application Number:
  US14/887,544
• Time in Patent Office: 483 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3221 of silicon bodies, e.g. for gettering
• CPC Class Codes: H01L 21/3225 Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering H01L21/3226 takes precedence
• CPC Class Codes: H01L 21/4817 for containers, e.g. caps H01L21/4871 takes precedence
• CPC Class Codes: H01L 21/54 Providing fillings in containers, e.g. gas fillings
• CPC Class Codes: H01L 23/041 the container being a hollow construction having no base used as a mounting for the semiconductor body
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/26 including materials for absorbing or reacting with moisture or other undesired substances , e.g. getters

Abstract

A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer.

Claims

1. A wafer for use in forming a wafer level package comprising:

a substrate having a seal structure formed on a portion of a surface of the substrate, the surface defined by a wafer level package (WLP) region and an external region, the seal structure forming a perimeter of the WLP region; and

a layer of getter material disposed on at least a portion of the external region of the surface of the substrate and outside the seal structure and the WLP region.

2. The wafer of claim 1, wherein the external region comprises a saw-to-reveal (STR) region.

3. The wafer of claim 2, wherein the STR region is defined by a two-dimensional pattern of intersecting horizontal and vertical saw lanes, and the layer of getter material is disposed on at least a portion of at least one of the horizontal and vertical saw lanes.

4. The wafer of claim 3, wherein the layer of getter material is disposed on at least a portion of both the horizontal and the vertical saw lanes.

5. The wafer of claim 2, wherein the STR region is defined by a series of parallel saw lanes.

6. The wafer of claim 2, wherein the layer of getter material is continuous.

7. The wafer of claim 1, wherein the substrate is a window cap wafer and at least a portion of the WLP region includes an optically transmissive window material.

8. The wafer of claim 1, wherein the substrate is a device wafer and at least a portion of the WLP region includes at least one semiconductor device.

9. The wafer of claim 1, wherein the layer of getter material is further disposed inside the seal structure and the WLP region on at least a portion of the WLP region.

10. The wafer of claim 1, wherein the getter material comprises at least one of titanium (Ti), zirconium (Zr), ruthenium (Ru), tantalum (Ta), hafnium (Hf), lanthanum (La) and molybdenum (Mo).

11. The wafer of claim 10, wherein the thickness of the layer of getter material is in a range of about 1000 Angstroms to about 10,000 Angstroms.

12. A method for forming a wafer comprising:

providing a substrate;

masking a surface of the substrate with a masking material to at least partially define an external region, wherein at least a portion of the external region is open to the surface of the substrate; and

depositing a layer of getter material on the surface of the substrate through the open portion of the external region.

13. The method of claim 12, wherein masking the surface with the masking material at least partially defines a WLP region separated from the external region, wherein at least a portion of the WLP region is open to the surface of the substrate, and the layer of getter material is further deposited on the surface of the substrate through the open portion of the WLP region.

14. The method of claim 12, wherein the external region comprises an STR region defined by at least one saw lane.

15. The method of claim 14, wherein depositing forms a continuous layer of getter material.

16. A method for forming a wafer level package, comprising:

providing a window cap wafer and a device wafer, each of the window cap wafer and the device wafer having a seal structure formed on a portion of a surface of the substrate, the substrate defined by a WLP region and an external region, the seal structure forming a perimeter of the WLP region, wherein a layer of getter material is disposed on at least a portion of the external region and outside the seal structure and the WLP region of at least one of the window cap wafer and the device wafer;

aligning the window cap wafer with the device wafer; and

bonding the window cap wafer and the device wafer to each other to form the wafer level package.

17. The method of claim 16, wherein during the bonding at least a portion of one or more impurities present on at least one of the window cap wafer and the device wafer outgas into the layer of getter material.

18. The method of claim 16, wherein the layer of getter material reduces pressure in a region between the window cap wafer and the device wafer during the bonding.

19. The method of claim 16, wherein the bonding is performed under vacuum and comprises heating the layer of getter material to a temperature such that it is activated during bonding.

20. The method of claim 19, wherein the layer of getter material is heated to a temperature of at least 300°

C.