Method of manufacturing package system
First Claim
1. A method of manufacturing a package system, the method comprising:
- forming a first interconnect structure over a first surface of a first substrate;
forming at least one first through silicon via (TSV) structure in the first substrate;
disposing the first substrate over a carrier with the first surface facing the carrier;
depositing a molding compound material over the carrier and around the first substrate;
forming at least one through via in the molding compound material, wherein the at least one through via is offset from the first substrate in a direction parallel to the first surface;
forming a second interconnect structure over a second surface of the first substrate;
removing the carrier to expose the first interconnect structure over the first surface of the first substrate; and
disposing a first integrated circuit over the first surface of the first substrate, the first integrated circuit being electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps.
1 Assignment
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Accused Products
Abstract
A method of manufacturing a package system includes forming a first interconnect structure over a first surface of a first substrate, forming at least one first through silicon via (TSV) structure in the first substrate, disposing the first substrate over a carrier with the first surface facing the carrier, depositing a molding compound material over the carrier and around the first substrate, forming a second interconnect structure over a second surface of the first substrate, removing the carrier to expose the first interconnect structure over the first surface of the first substrate, and disposing a first integrated circuit over the first surface of the first substrate. The first integrated circuit is electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps.
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Citations
20 Claims
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1. A method of manufacturing a package system, the method comprising:
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forming a first interconnect structure over a first surface of a first substrate; forming at least one first through silicon via (TSV) structure in the first substrate; disposing the first substrate over a carrier with the first surface facing the carrier; depositing a molding compound material over the carrier and around the first substrate; forming at least one through via in the molding compound material, wherein the at least one through via is offset from the first substrate in a direction parallel to the first surface; forming a second interconnect structure over a second surface of the first substrate; removing the carrier to expose the first interconnect structure over the first surface of the first substrate; and disposing a first integrated circuit over the first surface of the first substrate, the first integrated circuit being electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of manufacturing a package system, the method comprising:
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forming a first interconnect structure over a first surface of a first substrate; removably mounting the first substrate on a carrier with the first interconnect structure positioned between the first substrate and the carrier; depositing a molding compound material over the carrier and the first substrate; forming at least one through silicon via (TSV) structure through the first substrate along a first axis; opening at least one through via in the molding compound material along a second axis, wherein the second axis parallels the first axis and is separated from the first surface; forming a second interconnect structure over a second surface of the first substrate; and removing the carrier to expose the first interconnect structure. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A method of manufacturing a package system, the method comprising:
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forming a first multilayer interconnect structure over a first surface of a first substrate; mounting the first interconnect structure on a carrier; depositing a molding compound material over the carrier and around the first substrate; forming a first through silicon via (TSV) structure through the first substrate, the first TSV structure having a first depth; forming at least one through via in the molding compound material, the through via having a second depth at least equal to the first depth; forming a second interconnect structure over a second surface of the first substrate; removing the carrier to expose portions of the first interconnect structure; and mounting at least one integrated circuit on the exposed portions of the first interconnect structure.
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Specification