Method of manufacturing package system

• US 9,570,324 B2
• Filed: 05/06/2015
• Issued: 02/14/2017
• Est. Priority Date: 05/26/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Wei-Cheng, Hou, Shang-Yun, Jeng, Shin-Puu, Yu, Chen-Hua
• Primary Examiner(s): Menz, Laura
• Application Number:
  US14/705,555
• Publication Number:
  US 20150235873A1
• Time in Patent Office: 650 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05681 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/381 : Pitch distance

Abstract

A method of manufacturing a package system includes forming a first interconnect structure over a first surface of a first substrate, forming at least one first through silicon via (TSV) structure in the first substrate, disposing the first substrate over a carrier with the first surface facing the carrier, depositing a molding compound material over the carrier and around the first substrate, forming a second interconnect structure over a second surface of the first substrate, removing the carrier to expose the first interconnect structure over the first surface of the first substrate, and disposing a first integrated circuit over the first surface of the first substrate. The first integrated circuit is electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps.

Claims

1. A method of manufacturing a package system, the method comprising:

forming a first interconnect structure over a first surface of a first substrate;

forming at least one first through silicon via (TSV) structure in the first substrate;

disposing the first substrate over a carrier with the first surface facing the carrier;

depositing a molding compound material over the carrier and around the first substrate;

forming at least one through via in the molding compound material, wherein the at least one through via is offset from the first substrate in a direction parallel to the first surface;

forming a second interconnect structure over a second surface of the first substrate;

removing the carrier to expose the first interconnect structure over the first surface of the first substrate; and

disposing a first integrated circuit over the first surface of the first substrate, the first integrated circuit being electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps.

2. The method of claim 1, wherein the first integrated circuit comprises a second substrate, and a coefficient of thermal expansion (CTE) of the second substrate is substantially equal to a CTE of the first substrate.

3. The method of claim 2, further comprising:

disposing a second integrated circuit over the first substrate, wherein

the second integrated circuit is electrically coupled with the at least one first TSV structure,

the second integrated circuit comprises a third substrate, and

a CTE of the third substrate is substantially equal to the CTE of the first substrate.

4. The method of claim 1, wherein

the molding compound material has a first surface facing the first integrated circuit, and a second surface facing away from the first integrated circuit,

the first interconnect structure has a first surface facing the first integrated circuit,

the first surface of the molding compound material is flush with the first surface of the first interconnect structure, and

the second surface of the molding compound material is flush with a surface of the at least one first TSV structure.

5. The method of claim 1, wherein a metallic line pitch of the first interconnect structure is smaller than a metallic line pitch of the second interconnect structure.

6. The method of claim 1,

wherein

the at least one through via is electrically coupled with a portion of the first interconnect structure which extends over at least a portion of the molding compound material.

7. The method of claim 1, wherein:

the molding compound material extends between the second interconnect structure and the first substrate,

and the at least one first TSV structure is disposed through the molding compound layer and the first substrate.

8. The method of claim 1, further comprising:

disposing an interposer between the first integrated circuit and the first substrate, wherein

the interposer comprises at least one second TSV structure, and

the at least one second TSV structure is electrically coupled with the first integrated circuit and the at least one first TSV structure.

9. The method of claim 1, further comprising:

forming a third interconnect structure over the second surface of the first substrate, wherein the third interconnect structure includes a plurality of conductive patterns,

the third interconnect structure is between the second surface of the first substrate and the second interconnect structure, and

the molding compound material is formed around the first interconnect structure, the first substrate and the third interconnect structure.

10. The method of claim 9, wherein

a metallic line pitch of the third interconnect structure is larger than a metallic line pitch of the first interconnect structure and is smaller than a metallic line pitch of the second interconnect structure.

11. A method of manufacturing a package system, the method comprising:

forming a first interconnect structure over a first surface of a first substrate;

removably mounting the first substrate on a carrier with the first interconnect structure positioned between the first substrate and the carrier;

depositing a molding compound material over the carrier and the first substrate;

forming at least one through silicon via (TSV) structure through the first substrate along a first axis;

opening at least one through via in the molding compound material along a second axis, wherein the second axis parallels the first axis and is separated from the first surface;

forming a second interconnect structure over a second surface of the first substrate; and

removing the carrier to expose the first interconnect structure.

12. The method of claim 11, wherein opening the at least one through via comprises

forming an opening having a depth at least equal to a thickness of the first substrate structure;

and

filling the opening with a conductive material.

13. The method of claim 12, wherein

opening the at least one through via further comprises forming the at least one through via in direct electrical contact with the first interconnect structure.

14. The method of claim 11, further comprising:

mounting a second substrate on the first interconnect structure, and

mounting a first integrated circuit on the second substrate, wherein the second substrate includes at least one second through silicon via (TSV) structure for establishing electrical contact between the first integrated circuit and the first interconnect structure.

15. The method of claim 11, further comprising:

forming a third interconnect structure between the first substrate and the second interconnect structure, the first interconnect structure having a first conductive line pitch, the second interconnect structure having a second conductive line pitch and the third interconnect structure having a third conductive line pitch, wherein the first conductive line pitch and the third conductive line pitch are both smaller than the second conductive line pitch.

16. The method of claim 15, wherein

depositing the molding material comprises:

forming a first surface and an opposed second surface on the molding compound material, the first surface facing the first integrated circuit and the second surface facing away from the first integrated circuit,

aligning the first surface of the molding compound material with a surface of the first interconnect structure, and

aligning the second surface of the molding compound material with a surface of the third interconnect structure.

17. The method of claim 11, wherein:

forming the first interconnect structure comprises forming a first conductive pattern having a first conductive line pitch; and

forming the second interconnect structure comprises forming a second conductive pattern having a second conductive line pitch, wherein the first conductive line pitch is smaller than the second conductive line pitch.

18. The method of claim 13, further comprising

mounting the second interconnect structure on the second surface of the first substrate, wherein the at least one through via is in direct electrical contact with the second interconnect structure.

19. The method of claim 18, wherein:

forming the first interconnect structure comprises forming a first conductive line pattern having a width less than or equal to a width of the first substrate, and

forming the second interconnect structure comprises forming a second conductive line pattern having a width greater than the width of the first interconnect structure.

20. A method of manufacturing a package system, the method comprising:

forming a first multilayer interconnect structure over a first surface of a first substrate;

mounting the first interconnect structure on a carrier;

depositing a molding compound material over the carrier and around the first substrate;

forming a first through silicon via (TSV) structure through the first substrate, the first TSV structure having a first depth;

forming at least one through via in the molding compound material, the through via having a second depth at least equal to the first depth;

forming a second interconnect structure over a second surface of the first substrate;

removing the carrier to expose portions of the first interconnect structure; and

mounting at least one integrated circuit on the exposed portions of the first interconnect structure.