Semiconductor packages and related manufacturing methods

• US 9,570,381 B2
• Filed: 04/02/2015
• Issued: 02/14/2017
• Est. Priority Date: 04/02/2015
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Lu, Chun-Ting, Lin, Chun-Hung, Chen, Yi-Ting
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US14/677,863
• Publication Number:
  US 20160293531A1
• Time in Patent Office: 684 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/4828 Etching etching for cleaning without patterning H01L21/4835
• CPC Class Codes: H01L 21/4832 Etching a temporary substrate after encapsulation process to form leads
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49586 Insulating layers on lead frames
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

Described herein are semiconductor packages having an insulating layer and the manufacturing methods thereof, wherein semiconductor packages include a die pad; a plurality of leads surrounding the die pad, wherein each of the leads comprises an inner lead portion and an outer lead portion, and wherein at least one lead further comprises a trace portion; a chip disposed on the die pad and electrically connected to the leads; a molding compound encapsulating the chip, the inner lead portions and the trace portion, where the outer lead portions and a first surface of the trace portion are exposed from the molding compound; and an insulating layer covering the first surface of the trace portion.

Claims

1. A semiconductor package, comprising:

a die pad;

a plurality of leads surrounding the die pad, wherein each of the leads comprises an inner lead portion and an outer lead portion, and wherein at least one lead further comprises a trace portion;

a chip disposed on the die pad and electrically connected to ones of the plurality of leads;

a molding compound encapsulating the chip, the inner lead portions and the trace portion, wherein the outer lead portions and a bottom surface of the trace portion are exposed from the molding compound; and

an insulating layer covering the bottom surface of the trace portion, and wherein the insulating layer further covers a portion of a bottom surface of the molding compound.

2. The semiconductor package of claim 1, wherein the insulating layer exposes an area of the bottom surface of the trace portion adjacent to the outer lead portion of the at least one lead.

3. The semiconductor package of claim 2, wherein the exposed area of the bottom surface of the trace portion is tapered from the outer lead portion to the insulating layer.

4. The semiconductor package of claim 3, wherein the distance between the end of the taper of the exposed area of the bottom surface of the trace portion and the periphery of the outer lead portion is smaller than a width of the bottom surface of the trace portion.

5. The semiconductor package of claim 1, wherein the insulating layer further exposes a portion of the bottom surface of the molding compound.

6. The semiconductor package of claim 1, wherein a ratio of a width of the insulating layer to a width of the bottom surface of the trace portion is in a range of 1:

1 to 1.5;

1.

7. The semiconductor package of claim 1, wherein the outer lead portion extends past the bottom surface of the molding compound.

8. The semiconductor package of claim 7, wherein the insulating layer has a bottom surface, and wherein a first height of the outer lead portion is greater than a second height between the bottom surface of the insulating layer and the bottom surface of the trace portion, and the second height is less than a third height of a portion of the molding compound extending past the bottom surface of the trace portion.

9. The semiconductor package of claim 1, wherein the outer lead portion is an exposed surface, which is substantially coplanar with the bottom surface of the molding compound.

10. An electronic device, comprising:

a semiconductor package, comprising;

a die pad;

a plurality of leads surrounding the die pad, wherein each of the leads comprises an inner lead portion and an outer lead portion, and wherein at least one lead further comprises a trace portion;

a chip disposed on the die pad and electrically connected to ones of the plurality of leads;

a molding compound encapsulating the chip, the inner lead portions and the trace portion, wherein the outer lead portions and a bottom surface of the trace portion are exposed from the molding compound; and

an insulating layer covering the bottom surface of the trace portion, and wherein the insulating layer further covers a portion of a bottom surface of the molding compound; and

a printed circuit board attached to the semiconductor package and electrically connected to the semiconductor package.

11. The electronic device of claim 10, wherein the outer lead portion protrudes from the bottom surface of the molding compound.

12. The electronic device of claim 10, wherein the outer lead portion is an exposed surface substantially coplanar with the bottom surface of the molding compound.

13. The electronic device of claim 10, further comprising at least one interconnection element physically connecting to the outer lead portion, physically connecting to the printed circuit board, and contacting with an exposed area of the trace portion.

14. The electronic device of claim 10, wherein the insulating layer further exposes a portion of the bottom surface of the molding compound.

15. An electronic device, comprising:

a molding compound;

a die pad protruding from a bottom surface of the molding compound;

a die disposed on the die pad, the die encapsulated by the molding compound;

a plurality of leads surrounding the die pad, each of the plurality of leads comprising an inner lead portion and an outer lead portion, the inner lead portion encapsulated by the molding compound and the outer lead portion protruding from the bottom surface of the molding compound, and at least one lead of the plurality of leads further comprises a trace portion exposed at the bottom surface of the molding compound;

a printed insulating layer formed on the trace portion, wherein the printed insulating layer covers a portion of the bottom surface of the molding compound; and

a plurality of wires, each wire bonded to the die and to one of the plurality of inner lead portions, the plurality of wires encapsulated by the molding compound.

16. The electronic device of claim 15, wherein multiple leads of the plurality of leads including the at least one lead each comprises a trace portion such that a plurality of trace portions are exposed by the molding compound.

17. The electronic device of claim 16, wherein the trace portions extend from an area near the die pad to an inner ring of outer lead portions or to an outer ring of outer lead portions, the outer ring near a periphery of the electronic device.

18. The electronic device of claim 16, wherein each outer lead portion includes an outer lead surface, and wherein a pitch between two neighboring trace portions is smaller than a pitch between two neighboring outer lead surfaces.