Stacked packaging improvements

• US 9,570,416 B2
• Filed: 09/30/2015
• Issued: 02/14/2017
• Est. Priority Date: 11/03/2004
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Mitchell, Craig S., Beroz, Masud
• Primary Examiner(s): Le, Thao P
• Application Number:
  US14/870,827
• Publication Number:
  US 20160035692A1
• Time in Patent Office: 503 Days
• Field of Search: 257/678, 438/110
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1052 Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01002 : Helium [He]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A plurality of microelectronic assemblies are made by severing an in-process unit including an upper substrate and lower substrate with microelectronic elements disposed between the substrates. In a further embodiment, a lead frame is joined to a substrate so that the leads project from this substrate. Lead frame is joined to a further substrate with one or more microelectronic elements disposed between the substrates.

Claims

1. A microelectronic unit including upper and lower substrates and at least one microelectronic elements disposed between said upper and lower substrates, said upper substrate including a top surface and an opposed bottom surface facing toward said at least one microelectronic element, and said lower substrate including a top surface facing toward said at least one microelectronic element,

said upper substrate including a first region aligned with a second region of said lower substrate, said at least one said microelectronic element disposed therebetween,

said first and second regions having respective first and second electrically conductive elements, said first electrically conductive element of said first region being disposed at said bottom surface of said upper substrate and said second electrically conductive element of said second region being disposed at said top surface of said lower substrate, said upper substrate being electrically connected to said second electrically conductive element of the corresponding region of said lower substrate;

and

electrically conductive spacing elements joined to said first and second electrically conductive elements, said electrically conductive spacing elements disposed on opposed sides of said at least one microelectronic element and each having a height extending from said first conductive element to said second conductive element.

2. The microelectronic unit of claim 1, further comprising an encapsulant disposed between said upper and lower substrates.

10. The microelectronic element of claim 2, wherein said encapsulant is a molded encapsulant.

11. The microelectronic element of claim 2, wherein said electrically conductive spacing elements contact said electrically conductive elements of said first and second regions.

12. The microelectronic element of claim 1, wherein said plurality of electrically conductive spacing elements are solder balls.

13. The microelectronic element of claim 1, wherein said plurality of electronically conductive spacing elements are pins.

14. The microelectronic element of claim 1, further comprising first terminals disposed at a top surface of said upper substrate electrically connected with said second electrically conductive element.

15. The microelectronic element of claim 14, further comprising second terminals disposed at a bottom surface of said lower substrate that is opposite said top surface of said lower substrate.

20. The method of claim 12, wherein the solder ball further comprises:

a solder material having a first melting point; and

a core comprised of a material having a second melting point, the second melting point being greater than the first melting point.

3. A method of making a plurality of microelectronic assemblies comprising the steps of:

providing an in-process unit including a plurality of microelectronic elements, at least one upper substrate extending above the microelectronic elements and at least one lower substrate extending below the microelectronic elements, at least one of said substrates including a plurality of regions;

electrically connecting conductive elements on said upper and lower substrates with one another;

injecting an encapsulant between said upper and lower substrates;

and then

severing said in-process unit to form individual units, each said unit including a region of each of said at least one of said substrates and at least one of said microelectronic elements,

wherein both said upper substrate and said lower substrate include a plurality of regions, and wherein said step of severing is performed so that each said unit includes a portion of said upper substrate, a portion of said lower substrate and one or more microelectronic elements disposed between said substrates.

16. The method of claim 3, further comprising providing an electrically conductive spacing element between said at least one upper substrate and said at least one lower substrate.

17. The method of claim 16, wherein said electrically conductive spacing elements are solder balls.

18. The method of claim 16, wherein said electrically conductive spacing elements are pins.

19. The method of claim 3, further comprising positioning at least one microelectronic element of said plurality of microelectronic elements in each of said plurality of regions.

4. A microelectronic unit, comprising:

an upper dielectric element having first electrically conductive elements thereon;

a lower dielectric element having second electrically conductive elements thereon;

a microelectronic element disposed between said upper and lower dielectric elements; and

a plurality of electrically conductive spacing elements joined to said respective first and second conductive elements and electrically connecting said upper and lower dielectric elements, said electrically conductive spacing elements defining a spacing between said upper and lower substrates,

wherein an encapsulant is molded between the upper and lower dielectric elements.

5. The microelectronic unit as claimed in claim 4, wherein said electrically conductive spacing elements are solder balls, said encapsulant overlies said microelectronic element and at least substantially fills a volume between said upper and lower dielectric elements.

6. The microelectronic element of claim 5, wherein said upper dielectric element includes an upper surface and an opposed lower surface facing toward said microelectronic element, and said lower dielectric element includes an upper surface and an opposed lower surface facing away from said microelectronic element, said first electrically conductive elements being disposed at said opposed lower surface of said upper dielectric element, and said second electrically conductive elements being disposed at said upper surface of said lower dielectric element.

7. The microelectronic unit as claimed in claim 6, wherein said upper dielectric element has an upper surface facing away from said microelectronic element and upper terminals exposed at said upper surface, at least one of said upper terminals overlying a first major surface of said microelectronic element, and said lower dielectric element has a lower surface facing away from said microelectronic element and lower terminals exposed at said lower surface, wherein at least one of said lower terminals underlies a second major surface of said microelectronic element remote from said first major surface, said upper and lower terminals being electrically interconnected.

8. The microelectronic unit as claimed in claim 7, wherein at least some of said upper and lower terminals are electrically connected with said first and second conductive spacing elements.

9. The microelectronic element of claim 4, wherein said electrically conductive spacing elements are pins.