Wireless communicating among vertically arranged integrated circuits (ICs) in a semiconductor package

• US 9,570,420 B2
• Filed: 09/29/2011
• Issued: 02/14/2017
• Est. Priority Date: 09/29/2011
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Castaneda, Jesus Alfonso, Behzad, Arya Reza, Rofougaran, Ahmadreza, Zhao, Sam Ziqun, Boers, Michael
• Primary Examiner(s): Chen, Yu
• Application Number:
  US13/248,745
• Publication Number:
  US 20130082403A1
• Time in Patent Office: 1,965 Days
• Field of Search: 257/E23.142, 257/685, 257/686, 257/723, 257/724, 257/777, 257/786, 438/108, 438/109, 438/614, 438/612, 438/666
• US Class Current: 1/1
• CPC Class Codes: G02B 6/12002 Three-dimensional structures
• CPC Class Codes: G02B 6/43 Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06531 Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/1005 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01P 3/00 Waveguides; Transmission lines of the waveguide type
• CPC Class Codes: H01P 3/12 Hollow waveguides H01P3/20 takes precedence
• CPC Class Codes: H01P 3/121 integrated in a substrate
• CPC Class Codes: H04L 7/0091 : Transmitter details

Abstract

Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

Claims

1. An integrated circuit, comprising:

a first group of functional modules formed onto a first arrangement of useable fabrication layers in a horizontal direction;

a second group of functional modules formed onto a second arrangement of useable fabrication layers in the horizontal direction, wherein the first arrangement of useable fabrication layers and the second arrangement of useable fabrication layers are stacked in a vertical direction to form a vertical arrangement, the vertical direction being normal to the horizontal direction; and

a first conductive element formed within the first arrangement of useable fabrication layers and extending in the vertical direction, the first conductive element extending through the first arrangement of useable fabrication layers, and

a second conductive element formed within the second arrangement of useable fabrication layers and extending in the vertical direction, the second conductive element contacting the first conductive element and extending through the second arrangement of useable fabrication layers,

wherein the integrated circuit is configured and arranged to be displaced from a second integrated circuit having a third conductive element such that the first conductive element, the second conductive element, and the third conductive element are configured and arranged to form an integrated waveguide.

2. The integrated circuit of claim 1, wherein the first and the second arrangements of useable fabrication layers comprise:

a diffusion layer and a polysilicon layer to form components of the first group of functional modules; and

a conductive layer to form interconnections between the components.

3. The integrated circuit of claim 1, wherein the first arrangement of useable fabrication layers is interdigitated with a plurality of insulation layers, and

wherein an insulation layer from among the plurality of insulation layers is coupled to a useable fabrication layer from among the second arrangement of useable fabrication layers to form the vertical arrangement.

4. The integrated circuit of claim 1, wherein the first and the second arrangements of useable fabrication layers are coupled together using a physical connection.

5. The integrated circuit of claim 1, wherein a first portion of the first conductive element is formed within the first arrangement of useable fabrication layers and a second portion of the first conductive element is formed within the first arrangement of useable fabrication layers, the first portion being coupled to the second portion to form the first conductive element.

6. An integrated circuit, comprising:

a first group of functional modules formed onto a first arrangement of useable fabrication layers of a first semiconductor substrate;

a second group of functional modules formed onto a second arrangement of useable fabrication layers of a second semiconductor substrate, the first arrangement of useable fabrication layers being coupled to the second arrangement of useable fabrication layers to form a vertical arrangement; and

an integrated waveguide, formed laterally adjacent to the first and the second groups of functional modules and extending through the vertical arrangement in a vertical direction parallel to the first arrangement of useable fabrication layers and the second arrangement of useable fabrication layers of the vertical arrangement, configured to communicatively couple the first and the second groups of functional modules.

7. The integrated circuit of claim 6, wherein the integrated waveguide comprises:

a first conductive element communicatively coupled to the first group of functional modules; and

a second conductive element communicatively coupled to the second group of functional modules.

8. The integrated circuit of claim 7, wherein the first and the second conductive elements are configured and arranged to form a first parallel plate and a second parallel plate, respectively, and

wherein the first parallel plate and the second parallel plate are configured and arranged to form a parallel plate waveguide.

9. The integrated circuit of claim 8, wherein the first conductive element comprises:

a plurality of phase openings.

10. The integrated circuit of claim 9, wherein the plurality of phase openings are configurable to be opened or closed to dynamically configure operating characteristics of the integrated waveguide.

11. The integrated circuit of claim 10, wherein the first group of functional modules comprises:

a waveguide controller module configured to control whether each of the plurality of phase openings are to be opened or closed.

12. The integrated circuit of claim 7, wherein the first and the second conductive elements are characterized as being separated by a cavity region.

13. The integrated circuit of claim 7, wherein the cavity region is a region between the first conductive element and the second conductive element that is free of conductive material.

14. A Multichip Module (MCM), comprising:

a first integrated circuit including a first group of functional modules formed in a horizontal direction onto a first arrangement of useable fabrication layers of the first integrated circuit and a first conductive element, the first conductive element being formed in a vertical direction, normal to the horizontal direction, within the first arrangement of useable fabrication layers of the first integrated circuit; and

a second integrated circuit including a second conductive element, the second conductive element being vertically formed in the vertical direction within a second arrangement of useable fabrication layers of the second integrated circuit,

wherein the first integrated circuit is configured and arranged to be displaced from the second integrated circuit such that the first conductive element is communicatively coupled to the second conductive element to form an integrated waveguide.

15. The MCM of claim 14, wherein the first arrangement of useable fabrication layers comprises a first set of useable fabrication layers and a second set of useable fabrication layers,

wherein the first group of functional modules is formed onto the first set of useable fabrication layers of the first arrangement of useable fabrication layers;

and

wherein the first integrated circuit further includes;

a second group of functional modules formed onto the second set of useable fabrication layers of the first arrangement of useable fabrication layers, the first set of useable fabrication layers being coupled to the second set of useable fabrication layers to form a vertical arrangement.

16. The MCM of claim 15, wherein a first portion of the first conductive element is formed within the first arrangement of useable fabrication layers and a second portion of the first conductive element is formed within the first arrangement of useable fabrication layers, the first portion being coupled to the second portion to form the first conductive element.

17. The MCM of claim 14, wherein the first and the second integrated circuits are configured to communicate with each other using a multiple access transmission scheme.

18. The MCM of claim 14, wherein the first and the second integrated circuits are configured to wirelessly communicate with each other using the integrated waveguide.