Display device

• US 9,570,470 B2
• Filed: 07/09/2015
• Issued: 02/14/2017
• Est. Priority Date: 10/03/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Akimoto, Kengo, Komori, Shigeki, Uochi, Hideki, Futamura, Tomoya, Kasahara, Takahiro
• Primary Examiner(s): Sun, Yu-Hsi D
• Application Number:
  US14/795,602
• Publication Number:
  US 20150311235A1
• Time in Patent Office: 586 Days
• Field of Search: 257/43, 257/59, 257/72, 257/98, 349/43
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area is necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and whose end portions are over the first oxide semiconductor layer and overlap with the gate electrode. The gate electrode of the non-linear element is connected to a scan line or a signal line, the first wiring layer or the second wiring layer of the non-linear element is directly connected to the gate electrode layer so as to apply potential of the gate electrode.

Claims

1. A semiconductor device comprising:

a pixel portion over a substrate;

a protective circuit over the substrate, wherein the protective circuit is placed on an outside of the pixel portion;

a scan line electrically connected to the protective circuit; and

a common wiring electrically connected to the protective circuit,

wherein the protective circuit comprises a first transistor and a second transistor,

wherein one of a source and a drain of the first transistor is electrically connected to the scan line, a gate of the first transistor, and one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the common wiring, a gate of the second transistor, and the other of the source and the drain of the second transistor,

wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer comprising a channel region, and

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

2. The semiconductor device according to claim 1,

wherein a first conductive layer is electrically connected to the one of the source and the drain of the first transistor and the one of the source and the drain of the second transistor, and

wherein the first conductive layer is in contact with the scan line.

3. The semiconductor device according to claim 2,

wherein the first conductive layer and the common wiring are formed using the same layer.

4. The semiconductor device according to claim 1,

wherein a second conductive layer comprises the gate of the second transistor, and

wherein the second conductive layer is in contact with the common wiring.

5. The semiconductor device according to claim 4,

wherein the second conductive layer and the scan line are formed using the same layer.

6. The semiconductor device according to claim 1,

wherein the scan line comprises the gate of the first transistor.

7. A semiconductor device comprising:

a pixel portion over a substrate;

a protective circuit over the substrate, wherein the protective circuit is placed on an outside of the pixel portion;

a scan line electrically connected to the protective circuit; and

a common wiring electrically connected to the protective circuit,

wherein the protective circuit comprises a first transistor, a second transistor, and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to the scan line and a gate of the first transistor,

wherein one of a source and a drain of the second transistor is electrically connected to the common wiring and a gate of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to the scan line,

wherein the other of the source and the drain of the third transistor is electrically connected to the common wiring,

wherein a gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor,

wherein each of the first transistor, the second transistor, and the third transistor comprises an oxide semiconductor layer comprising a channel region, and

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

8. The semiconductor device according to claim 7,

wherein a first conductive layer comprises the gate of the first transistor,

wherein the first conductive layer is in contact with the scan line, and

wherein a second conductive layer comprises the gate of the third transistor.

9. The semiconductor device according to claim 8,

wherein the first conductive layer, the second conductive layer, and the common wiring are formed using the same layer.

10. The semiconductor device according to claim 8,

wherein a third conductive layer is electrically connected to the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor, and

wherein the second conductive layer and the third conductive layer are in contact with each other.

11. The semiconductor device according to claim 7,

wherein a third conductive layer is electrically connected to the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor,

wherein a fourth conductive layer is electrically connected to the one of the source and the drain of the second transistor and the other of the source and the drain of the third transistor, and

wherein the fourth conductive layer is in contact with the common wiring.

12. The semiconductor device according to claim 11,

wherein the third conductive layer, the fourth conductive layer, and the scan line are formed using the same layer.

13. The semiconductor device according to claim 7,

wherein the common wiring comprises the gate of the second transistor.

14. A semiconductor device comprising:

a pixel portion over a substrate;

a protective circuit over the substrate, wherein the protective circuit is placed on an outside of the pixel portion;

a scan line electrically connected to the protective circuit; and

a common wiring electrically connected to the protective circuit,

wherein the protective circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to the common wiring, a gate of the second transistor, and one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the scan line, a gate of the first transistor, and the other of the source and the drain of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to the common wiring, a gate of the fourth transistor, and one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the scan line, a gate of the third transistor, and the other of the source and the drain of the fourth transistor,

wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises an oxide semiconductor layer comprising a channel region, and

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

15. The semiconductor device according to claim 14,

wherein a first conductive layer is electrically connected to the one of the source and the drain of the first transistor and the one of the source and the drain of the second transistor,

wherein a second conductive layer comprises the gate of the first transistor,

wherein a third conductive layer is electrically connected to the one of the source and the drain of the third transistor and the one of the source and the drain of the fourth transistor,

wherein a fourth conductive layer comprises the gate of the third transistor.

16. The semiconductor device according to claim 15,

wherein each of the first conductive layer and the third conductive layer is in contact with the common wiring.

17. The semiconductor device according to claim 15,

wherein each of the second conductive layer and the fourth conductive layer is in contact with the scan line.

18. The semiconductor device according to claim 15,

wherein the first conductive layer, the third conductive layer, and the scan line are formed using the same layer.

19. The semiconductor device according to claim 15,

wherein the second conductive layer, the fourth conductive layer, and the common wiring are formed using the same layer.

20. The semiconductor device according to claim 14,

wherein the common wiring comprises the gate of the second transistor and the gate of the fourth transistor.

21. A semiconductor device comprising:

a pixel portion over a substrate;

a protective circuit over the substrate, wherein the protective circuit is placed on an outside of the pixel portion;

a scan line electrically connected to the protective circuit; and

a common wiring electrically connected to the protective circuit,

wherein the protective circuit comprises a first transistor and a second transistor,

wherein one of a source and a drain of the first transistor is electrically connected to the scan line, a gate of the first transistor, and one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the common wiring, a gate of the second transistor, and the other of the source and the drain of the second transistor,

wherein each of the first transistor and the second transistor comprises a first oxide semiconductor layer and a second oxide semiconductor layer,

wherein the second oxide semiconductor layer has higher electrical conductivity than the first oxide semiconductor layer, and

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc.

22. The semiconductor device according to claim 21,

wherein a first conductive layer is electrically connected to the one of the source and the drain of the first transistor and the one of the source and the drain of the second transistor, and

wherein the first conductive layer is in contact with the scan line.

23. The semiconductor device according to claim 22,

wherein the first conductive layer and the common wiring are formed using the same layer.

24. The semiconductor device according to claim 21,

wherein a second conductive layer comprises the gate of the second transistor, and

wherein the second conductive layer is in contact with the common wiring.

25. The semiconductor device according to claim 24,

wherein the second conductive layer and the scan line are formed using the same layer.

26. The semiconductor device according to claim 21,

wherein the scan line comprises the gate of the first transistor.