Semiconductor device and manufacturing method thereof

• US 9,570,484 B2
• Filed: 10/20/2014
• Issued: 02/14/2017
• Est. Priority Date: 01/12/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US14/518,125
• Publication Number:
  US 20150037934A1
• Time in Patent Office: 848 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/467 using masks
• CPC Class Codes: H01L 21/469 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques encapsulating layers H01L21/56; After-treatment of these layers
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

The semiconductor device includes a gate electrode over a substrate, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A length of part of an outer edge of the oxide semiconductor layer from an outer edge of the source electrode to an outer edge of the drain electrode is more than three times, preferably more than five times as long as a channel length of the semiconductor device. Further, oxygen is supplied from the gate insulating layer to the oxide semiconductor layer by heat treatment. In addition, an insulating layer is formed after the oxide semiconductor layer is selectively etched.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate;

forming a gate insulating layer over the gate electrode;

forming an oxide semiconductor layer over the gate insulating layer;

performing heat treatment on the oxide semiconductor layer;

forming a source electrode and a drain electrode over the oxide semiconductor layer after the heat treatment;

forming a resist mask over the oxide semiconductor layer;

performing etching on the oxide semiconductor layer using the resist mask; and

forming an insulating layer so as to cover the oxide semiconductor layer, the source electrode, and the drain electrode after performing the etching,

wherein the resist mask overlaps with the gate electrode, the source electrode and the drain electrode, and

wherein part of the source electrode and part of the drain electrode, the part not overlapping with the resist mask, are also used as masks for the etching.

2. The method for manufacturing a semiconductor device, according to claim 1, wherein the gate insulating layer contains excessive oxygen with respect to a stoichiometry proportion.

3. The method for manufacturing a semiconductor device, according to claim 1, wherein oxygen is supplied from the gate insulating layer to the oxide semiconductor layer by the heat treatment.

4. The method for manufacturing a semiconductor device, according to claim 1, wherein the heat treatment is performed at higher than or equal to 300°

C. and lower than or equal to 450°

C.

5. The method for manufacturing a semiconductor device, according to claim 1, wherein the oxide semiconductor layer comprises at least one element selected from In, Ga, Sn, and Zn.

6. The method for manufacturing a semiconductor device, according to claim 1, wherein the oxide semiconductor layer is non-single-crystal.

7. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate;

forming a gate insulating layer over the gate electrode;

forming an oxide semiconductor layer over the gate insulating layer;

forming a first insulating layer overlapping with the gate insulating layer with the oxide semiconductor layer interposed therebetween;

performing heat treatment on the oxide semiconductor layer and the first insulating layer;

forming a source electrode and a drain electrode over the oxide semiconductor layer and the first insulating layer;

forming a resist mask over the oxide semiconductor layer, the first insulating layer, the source electrode and the drain electrode;

performing etching on the oxide semiconductor layer using the resist mask; and

forming a second insulating layer so as to cover the oxide semiconductor layer after performing the etching,

wherein the resist mask overlaps with the gate electrode, and

wherein part of the source electrode and part of the drain electrode are also used as masks for the etching.

8. The method for manufacturing a semiconductor device, according to claim 7, wherein the gate insulating layer contains excessive oxygen with respect to a stoichiometry proportion.

9. The method for manufacturing a semiconductor device, according to claim 7, wherein oxygen is supplied from the gate insulating layer and the first insulating layer to the oxide semiconductor layer by the heat treatment.

10. The method for manufacturing a semiconductor device, according to claim 7, wherein the heat treatment is performed at higher than or equal to 300°

C. and lower than or equal to 450°

C.

11. The method for manufacturing a semiconductor device, according to claim 7, wherein the oxide semiconductor layer comprises at least one element selected from In, Ga, Sn, and Zn.

12. The method for manufacturing a semiconductor device, according to claim 7, wherein the oxide semiconductor layer is non-single-crystal.