High voltage trench transistor

• US 9,570,545 B2
• Filed: 04/22/2015
• Issued: 02/14/2017
• Est. Priority Date: 09/21/2011
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Dong, Yemin, Yi, Liang, Liu, Zhanfeng, Verma, Purakh Raj, Nambatyathu, Ramadas
• Primary Examiner(s): Sandvik, Benjamin
• Assistant Examiner(s): ASSOUMAN, HERVE-LOUIS Y
• Application Number:
  US14/692,768
• Publication Number:
  US 20150236085A1
• Time in Patent Office: 664 Days
• Field of Search: 257/329, 257/337, 257/339, 257/343, 257/140, 257/192, 257/368, 257/288, 257/488, 257/491
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region.

Claims

1. A semiconductor device comprising:

a substrate defined with a device region;

a first device doped well within the substrate, wherein the first device doped well encompasses the device region;

a gate disposed in the substrate, wherein the gate comprises a gate electrode and a first gate dielectric layer disposed in a first trench, wherein the first trench defines an upper trench portion;

a second trench disposed within the gate, wherein the second trench extends below the upper trench portion and defines a lower trench portion;

a second gate dielectric layer disposed in the second trench, wherein the second gate dielectric layer at least lines the lower trench portion;

a field plate disposed in the second trench, wherein the field plate fills the trench and is disposed adjacent to the gate;

first and second diffusion regions disposed within the device region, wherein the gate is displaced from the second diffusion region; and

wherein the first device doped well surrounds the upper and lower trench portions and extends to a depth below the lower trench portion, the first device doped well includes same polarity type dopants as the first and second diffusion regions.

2. The semiconductor device of claim 1 comprising second and third device doped wells disposed within the first device doped well, wherein the second and third device doped wells are adjacent to first and second sides of the first trench and include a depth shallower than the upper trench portion.

3. The semiconductor device of claim 1 comprising an intermediately doped region within the first device doped well, wherein the intermediately doped region is disposed below the gate and includes same polarity type dopants as the first device doped well.

4. The semiconductor device of claim 1 wherein the second gate dielectric layer isolates the field plate from the gate in the upper trench portion and wraps around the field plate in the lower trench portion.

5. The semiconductor device of claim 3 wherein the intermediately doped well surrounds a lower portion of the second gate dielectric layer.

6. The semiconductor device of claim 3 wherein the intermediately doped well is disposed from about a bottom edge of the upper trench portion to about a bottom edge of the lower trench portion.

7. A semiconductor device comprising:

a substrate defined with a device region;

a first device doped well within the substrate, wherein the first device doped well encompasses the device region;

a gate having a gate electrode and first and second gate dielectric layers disposed in a trench in the substrate, wherein the trench comprises upper and lower trench portions, wherein the first gate dielectric layer lines the upper trench portion and the second gate dielectric layer extends through the upper trench portion and lines the lower trench portion;

a field plate disposed in the upper and lower trench portions, wherein the field plate is disposed adjacent to the gate and extends below the gate;

source and drain regions disposed within the device region, wherein the gate is displaced from the drain region; and

wherein the first device doped well surrounds the upper and lower trench portions and extends to a depth below the lower trench portion, the first device doped well includes same polarity type dopants as the source and drain regions.

8. The semiconductor device of claim 7 comprising second and third device doped wells disposed within the first device doped well, wherein the second and third device doped wells include a depth shallower than the upper trench portion.

9. The semiconductor device of claim 8 wherein the first device doped well comprises first polarity type dopants and the third device doped well comprises second polarity type dopants different from the first polarity type.

10. The semiconductor device of claim 8 comprising a buried doped region in the substrate, wherein the buried doped region is disposed in the first device doped well and below the lower trench portion.

11. The semiconductor device of claim 10 wherein the buried doped region surrounds a lower portion of the field plate and second gate dielectric layer in the lower trench portion.

12. The semiconductor device of claim 11 wherein the second gate dielectric layer isolates the field plate from the gate electrode in the upper trench portion and wraps around the field plate in the lower trench portion.

13. The semiconductor device of claim 7 wherein the gate is laterally displaced from the drain region by at least the first gate dielectric layer, second gate dielectric layer and field plate.

14. The semiconductor device of claim 8 comprising a double diffused drain (DDD) doped well in the first device doped well.

15. The semiconductor device of claim 14 wherein the DDD doped well is disposed from about a bottom edge of the upper trench portion to about a bottom edge of the lower trench portion.

16. The semiconductor device of claim 7 wherein the second gate dielectric layer isolates the field plate from the gate electrode in the upper trench portion and lines sidewalls of the lower trench portion.

17. The semiconductor device of claim 9 wherein:

the source region is disposed adjacent to the gate and within the third device doped well; and

the drain region is disposed below the upper trench portion and is contiguous to a bottom edge of the lower trench portion.

18. The semiconductor device of claim 7 wherein the device region is surrounded by a device isolation region.

19. The semiconductor device of claim 18 wherein the device region comprises one or more internal device isolation regions, dividing the device region into multiple device sub-regions.

20. The semiconductor device of claim 19 comprising a low voltage device in the multiple device sub-regions, wherein the low voltage device comprises:

a gate having a gate electrode and gate dielectric disposed on the substrate;

source/drain regions disposed in the substrate adjacent to the gate; and

a channel region disposed in the substrate under the gate between the source/drain regions.