Source and drain process for FinFET

• US 9,570,567 B1
• Filed: 12/30/2015
• Issued: 02/14/2017
• Est. Priority Date: 12/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
• Primary Examiner(s): Dang, Trung Q
• Application Number:
  US14/984,514
• Time in Patent Office: 412 Days
• Field of Search: 257/401, 438/283
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02068 during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A FinFET includes a substrate, a fin structure, a dielectric layer, a metal gate, two spacers, a source and a drain. The fin structure is disposed on the substrate. The dielectric layer is disposed on the fin structure and covers two opposite side surfaces of the fin structure. The dielectric layer includes two first portions protruding from the side surfaces of the fin structure, such that two opposite first recesses are formed in the dielectric layer. The metal gate is disposed on a second portion of the dielectric layer which is sandwiched between the first portions. The spacers are disposed on the first portions of the dielectric layer and protrude from the first portions of the dielectric layer respectively, such that two second recesses are formed in the spacers. The source and drain are respectively disposed in the first recesses and the second recesses on the substrate.

Claims

1. A method for manufacturing a FinFET, the method comprising:

forming a fin structure on a substrate;

forming a dielectric layer on a top surface and two side surfaces of the fin structure, wherein the side surfaces are connected to two opposite edges of the top surface, and the fin structure and the dielectric layer are formed from different materials;

forming a dummy gate on a first portion of the dielectric layer;

forming two spacers respectively on two opposite sidewalls of the dummy gate, wherein an operation of forming the spacers comprises forming the spacers respectively on two second portions of the dielectric layer and exposing two third portions of the dielectric layer, wherein each of the second portions of the dielectric layer is located between the first portion and one of the third portions of the dielectric layer;

performing a first etching operation on the dielectric layer and the fin structure to remove the third portions and a portion of each of the second portions of the dielectric layer, and two first portions of the fin structure underlying the third portions and the portions of the second portions of the dielectric layer, thereby forming two first recesses respectively in the spacers; and

performing a second etching operation on the fin structure to remove two second portions of the fin structure which are respectively adjacent to the first portions of the fin structure, thereby forming two second recesses in the dielectric layer, wherein the second recesses respectively communicate with the first recesses.

2. The method of claim 1, wherein an operation of forming the fin structure forms the fin structure from silicon, and an operation of forming the dielectric layer forms the dielectric layer from silicon oxide.

3. The method of claim 1, wherein the operation of forming the spacers forms the spacers from silicon nitride.

4. The method of claim 1, wherein an operation of forming the dummy gate forms the dummy gate from polysilicon.

5. The method of claim 1, the method further comprising performing a wet clean operation on the first recesses and the second recesses after the second etching operation is completed.

6. The method of claim 1, the method further comprising performing an epitaxy operation on the substrate to form a source in one of the first recesses and one of the second recesses on the substrate, and to form a drain in the other one of the first recesses and the other one of the second recesses on the substrate after the second etching operation is completed.

7. The method of claim 6, wherein the epitaxy operation forms the source and the drain each of which comprises a silicon germanium (SiGe) layer.

8. The method of claim 6, the method further comprising replacing the dummy gate with a metal gate after the epitaxy operation is completed.

9. A method for manufacturing a FinFET, the method comprising:

forming a fin structure on a substrate;

forming a dielectric layer on a top surface and two side surfaces of the fin structure, wherein the side surfaces are connected to two opposite edges of the top surface, and the fin structure and the dielectric layer are formed from different materials;

forming a dummy gate on a first portion of the dielectric layer;

forming two spacers respectively on two opposite sidewalls of the dummy gate, wherein an operation of forming the spacers comprises forming the spacers respectively on two second portions of the dielectric layer and exposing two third portions of the dielectric layer, wherein each of the second portions of the dielectric layer is located between the first portion and one of the third portions of the dielectric layer;

performing a first etching operation on the dielectric layer and the fin structure to remove the third portions of the dielectric layer, a portion of each of the second portions of the dielectric layer, and two first portions of the fin structure underlying the third portions of the dielectric layer and the portions of the second portions of the dielectric layer, thereby forming two first recesses respectively in the spacers;

performing a second etching operation on the fin structure to remove two second portions of the fin structure which are respectively adjacent to the first portions of the fin structure, thereby forming two second recesses in the dielectric layer, wherein the second recesses respectively communicate with the first recesses;

performing a wet clean operation on the first recesses and the second recesses; and

performing an epitaxy operation on the substrate to form a source in one of the first recesses and one of the second recesses on the substrate, and to form a drain in the other one of the first recesses and the other one of the second recesses on the substrate.

10. The method of claim 9, wherein an operation of forming the fin structure forms the fin structure from silicon, and an operation of forming the dielectric layer forms the dielectric layer from silicon oxide.

11. The method of claim 9, wherein the operation of forming the spacers forms the spacers from silicon nitride.

12. The method of claim 9, wherein an operation of forming the dummy gate forms the dummy gate from polysilicon.

13. The method of claim 9, wherein the epitaxy operation is performed to form the source and the drain each of which comprises a silicon germanium (SiGe) layer.

14. The method of claim 9, wherein an operation of forming the fin structure is performed by recessing the substrate.

15. The method of claim 9, the method further comprising replacing the dummy gate with a metal gate after the epitaxy operation is completed.

16. A FinFET comprising:

a substrate;

a fin structure on the substrate;

a dielectric layer which is disposed on the fin structure and covers a top surface and two opposite side surfaces of the fin structure, wherein the dielectric layer comprises two first portions protruding from the side surfaces of the fin structure such that two first recesses are formed in the dielectric layer, each of the first recesses is surrounded by the dielectric layer and the substrate, and the first recesses are opposite to each other;

a metal gate on a second portion of the dielectric layer, wherein the second portion is sandwiched between the first portions of the dielectric layer;

two spacers on the first portions of the dielectric layer respectively, wherein the spacers respectively protrude from the first portions of the dielectric layer such that two second recesses are formed in the spacers;

a source which is disposed in one of the first recesses and one of the second recesses on the substrate; and

a drain which is disposed in the other one of the first recesses and the other one of the second recesses on the substrate.

17. The FinFET of claim 16, wherein the fin structure is formed from silicon, and the dielectric layer is formed from silicon oxide.

18. The FinFET of claim 16, wherein the spacers are formed from silicon nitride.

19. The FinFET of claim 16, wherein the source and the drain are formed from silicon germanium.

20. The FinFET of claim 16, wherein each of the source and the drain comprises an epitaxy layer.