Method for forming a semiconductor device having insulating parts or layers formed via anodic oxidation

• US 9,570,576 B2
• Filed: 12/10/2013
• Issued: 02/14/2017
• Est. Priority Date: 12/10/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Meiser, Andreas, Mauder, Anton, Zundel, Markus, Schulze, Hans-Joachim, Hirler, Franz, Weber, Hans
• Primary Examiner(s): NGUYEN, DUY T V
• Application Number:
  US14/102,290
• Publication Number:
  US 20150162418A1
• Time in Patent Office: 1,162 Days
• Field of Search: 438/138, 438/294, 438/459
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02258 formation by anodic treatment, e.g. anodic oxidation
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A method for forming a semiconductor device includes forming an electrical structure at a main surface of a semiconductor substrate and carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate.

Claims

1. A method for forming a semiconductor device, the method comprising:

forming an electrical structure at a main surface of a semiconductor substrate;

carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate after forming the electrical structure at the main surface; and

forming an electrically conductive layer at the back side of the semiconductor substrate, wherein a first part of the electrically conductive layer is directly separated from the back side surface of the semiconductor substrate by the oxide layer formed by the anodic oxidation and a second part of the electrically conductive layer is formed directly on the back side surface of the semiconductor substrate.

2. A method for forming a semiconductor device, the method comprising:

forming an electrical structure at a main surface of a semiconductor substrate;

carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate; and

forming an electrically conductive layer at the back side of the semiconductor substrate, wherein at least a part of the electrically conductive layer is directly separated from the back side surface of the semiconductor substrate by the oxide layer formed by the anodic oxidation;

wherein the oxide layer remains at least at an edge termination region surrounding the semiconductor substrate, wherein the edge termination region is a region extending from an edge of the semiconductor substrate laterally towards an emitter region of an insulated gate bipolar transistor or a drain region of a metal oxide semiconductor transistor located at the back side within the semiconductor substrate.

3. A method for forming a semiconductor device, the method comprising:

forming an electrical structure at a main surface of a semiconductor substrate;

carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate; and

forming a p-doped region adjacent to an n-doped region at the back side surface of the semiconductor substrate before the anodic oxidation, wherein the oxide layer in a first portion of the back side surface extending along the n-doped region has a greater thickness than the oxide layer in a second portion of the back side surface extending along the p-doped region,

wherein the electrical structure at the main surface is more complex than the p-doped region and the n-doped region formed at the back side surface.

4. The method according to claim 3, further comprising removing the oxide layer within the second portion.

5. The method according to claim 3, comprising implanting dopants at the first portion and the second portion to form a stepped field stop region at least at the second portion.

6. A method for forming a semiconductor device, the method comprising:

forming an electrical structure at a main surface of a semiconductor substrate;

carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate after forming the electrical structure at the main surface; and

forming a field effect transistor structure at the back side of the semiconductor substrate, wherein the oxide layer forms a gate oxide of the field effect transistor structure at the back side.