Gate stack and contact structure

• US 9,570,615 B2
• Filed: 10/28/2015
• Issued: 02/14/2017
• Est. Priority Date: 01/03/2014
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Zang, Hui
• Primary Examiner(s): Li, Meiya
• Assistant Examiner(s): Albrecht, Peter M
• Application Number:
  US14/924,925
• Publication Number:
  US 20160049514A1
• Time in Patent Office: 475 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02057 Cleaning during device manufacture
• CPC Class Codes: H01L 21/02112 characterised by the material of the layer
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A process for fabrication of semiconductor devices, particularly FinFETs, having a low contact horizontal resistance and a resulting device are provided. Embodiments include: providing a substrate having source and drain regions separated by a gate region; forming a gate electrode having a first length on the gate region; forming an epitaxy layer on the source and drain regions; forming a contact layer having a second length, longer than the first length, at least partially on the epitaxy layer; and forming an oxide layer on top and side surfaces of the contact layer for at least the first length.

Claims

1. A device comprising:

a substrate having a source region and a drain region separated along a first direction by a gate region, a thickness of the substrate defining a thickness direction;

a gate electrode having a first maximum length, along a second direction, the gate electrode being on the gate region, the second direction being perpendicular to both the first direction and the thickness direction;

an epitaxy layer on the source region and the drain region;

a first contact layer having a second maximum length along the second direction, the second maximum length being longer than the first maximum length, the first contact layer being at least partially on the epitaxy layer; and

an oxide layer on a top surface and side surfaces of the first contact layer for at least the first maximum length.

2. The device according to claim 1, wherein the gate electrode comprises:

a metal gate;

a high-k dielectric on side surfaceas and a bottom surface of the metal gate;

a nitride layer on side surfaces of the high-k dielectric; and

a second contact layer on the metal gate for the first maximum length.

3. The device according to claim 2, wherein:

the oxide layer separates the first contact layer and the second contact layer; and

the oxide layer and the nitride layer separate the first contact layer and the metal gate.

4. The device according to claim 2, wherein:

the metal gate, the first contact layer and the second contact layer each comprise tungsten (W); and

the metal gate comprises a titanium carbide (TiC) work function metal.

5. The device according to claim 4, further comprising:

a low-k dielectric layer having a first and a second portion over the drain region and the source region, respectively, the first portion and the second portion of the low-k dielectric layer being on the oxide layer,

wherein the second contact layer is disposed on the gate electrode and between the first portion and the second portion of the low-k dielectric layer, the second contact layer extending over the drain region and the source region over the first maximum length and being separated from the first contact layer by the oxide layer.

6. The device according to claim 1, further comprising:

a shallow trench isolation (STI) region in the substrate horizontally beyond the epitaxy layer, the first contact layer extending over the STI region;

a vertical portion of the first contact layer over the STI region; and

a second contact layer on the gate region.

7. The device according to claim 6, further comprising:

a horizontal portion of the first contact layer on the epitaxy layer and having a thickness of 20 nanometers (nm) to 100 nm; and

a portion of the second contact layer extending horizontally over the source region and drain region and having a thickness of 20 nm to 400 nm.

8. The device according to claim 6, further comprising:

a low-k dielectric layer separating the vertical portion of the first contact layer from the second contact layer.

9. A device comprising:

a substrate having a source region and a drain region separated along a first direction by a gate region, a thickness of the substrate defining a thickness direction;

a gate electrode having a first maximum horizontal length along a second direction, the gate electrode being on the gate region and having a first height, the second direction being perpendicular to both the first direction and the thickness direction;

an epitaxy layer on the source region and the drain region;

a shallow trench isolation (STI) region in the substrate horizontally beyond the epitaxy layer;

a tungsten (W) contact layer having a second maximum horizontal length along the second direction, the second maximum horizontal length being longer than the first maximum horizontal length, the tungsten contact layer having a second height less than the first height and being at least partially on the epitaxy layer, the tunsten contact layer extending horizontally over the STI region and comprising a vertical portion over the STI region, the tungsten contact layer being a first contact layer; and

an oxide layer on a top surface and side surfaces of the first contact layer for at least the first maximum horizontal length.

10. The device according to claim 9, wherein the gate electrode comprises:

a metal gate;

a high-k dielectric on side surfaces and a bottom surface of the metal gate;

a nitride layer on side surfaces of the high-k dielectric; and

a second contact layer on the metal gate for the first maximum horizontal length.

11. The device according to claim 10, wherein:

the oxide layer separates the first contact layer and the second contact layer; and

the oxide layer and the nitride layer separate the first contact layer and the metal gate.

12. The device according to claim 9, further comprising:

a low-k dielectric layer having a first portion and a second portion over the drain region and the source region, respectively, the first portion and the second portion of the low-k dielectric layer being on the oxide layer; and

a second contact layer on the gate electrode and between the first portion and The second portion of the low-k dielectric layer, the second contact layer extending over the drain region and the source region over the first maximum horizontal length and being separated from the first contact layer by the oxide layer.