Integrated level shifter

• US 9,570,927 B2
• Filed: 06/02/2015
• Issued: 02/14/2017
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel M., Sharma, Santosh, Zhang, Ju Jason
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US14/728,874
• Publication Number:
  US 20160079964A1
• Time in Patent Office: 623 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02M 1/0048 : Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/088 : for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/155 : using semiconductor devices only
• CPC Class Codes: H02M 3/157 : with digital control
• CPC Class Codes: H02M 3/1584 : with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1588 : comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/102 : in field-effect transistor switches
• CPC Class Codes: H03K 19/018507 : Interface arrangements
• CPC Class Codes: H03K 3/012 : Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356017 : using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: Y02B 40/00 : Technologies aiming at improving the efficiency of home appliances, e.g. induction cooking or efficient technologies for refrigerators, freezers or dish washers
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Claims

1. A level shift circuit comprising:

a GaN-based level shift transistor, comprising;

a gate connected to a gate terminal,

a drain connected to a drain terminal, and

a source connected to a source terminal,

wherein the level shift transistor is configured to receive an input referenced to a ground at the gate terminal and to generate an output at the drain terminal, wherein the output is referenced to a floating voltage, and

wherein at least a portion of the drain terminal is shielded from the substrate by a shield metal between the substrate and the portion of the drain terminal.

2. The semiconductor device of claim 1, wherein the level shift transistor is operated with a pulsed input signal, and wherein a duration of the pulsed input signal is less than 100 nanoseconds.

3. The semiconductor device of claim 1, wherein a channel width of the level shift transistor is less than 100 microns.

4. The semiconductor device of claim 1, wherein the drain of the level shift transistor is less than 100 microns from a bond pad.

5. The semiconductor device of claim 1, wherein the level shift transistor includes a source ohmic contact area connected to the source terminal, and the source terminal is connected to a metal pad that is immediately adjacent to the source terminal and is more than 100 times the source ohmic contact area.

6. The semiconductor device of claim 1, wherein the level shift transistor includes a drain ohmic contact area connected to the drain terminal, and the drain terminal is connected to a metal pad that is immediately adjacent to the drain terminal and is more than 100 times the drain ohmic contact area.

7. The semiconductor device of claim 1, The semiconductor device of claim 1 wherein the level shift transistor comprises a source area and a drain area and the source area does not encircle the drain area.

8. The semiconductor device of claim 1, wherein the level shift transistor comprises an active region having a source area at a first end and a drain area at an opposing end.

9. The level shift circuit of claim 1 comprising a transistor having an Idsat to Qoss ratio greater than one ampere per nanocoulomb.

10. The level shift circuit of claim 1 comprising a first capacitance between the drain terminal and the floating voltage, wherein the first capacitance is configured to prevent a change of output state when the floating voltage changes voltage potential from ground to a maximum allowed voltage.

11. The level shift circuit of claim 1 comprising an electrically conductive circuit element coupled between the source and the ground.

12. The level shift circuit of claim 1 comprising an electrically conductive circuit element coupled between the drain and a positive side of a power source that is referenced to the floating voltage.

13. The level shift circuit of claim 1 comprising a first circuit portion disposed on a first GaN device and a second circuit portion disposed on a second GaN device.

14. The level shift circuit of claim 13 wherein the first circuit portion comprises the output and the second circuit portion comprises a receiver circuit, and a bond wire forms an electrical connection between the output and the receiver circuit.

15. The level shift circuit of claim 13 wherein at least one level shift transistor and all ground referenced circuit elements of the level shift circuit are disposed on the first GaN device.

16. The level shift circuit of claim 15 comprising a low side power switch disposed on the first GaN device.

17. The level shift circuit of claim 13 wherein the second circuit portion comprises an electrically conductive circuit element coupled between the drain and a positive side of a power source that is referenced to the floating voltage.

18. The shift circuit of claim 17 comprising a high side power switch integrated on the same device.

19. A level shift circuit comprising:

a GaN-based level shift transistor, comprising;

a gate connected to a gate terminal,

a drain connected to a drain terminal, and

a source connected to a source terminal,

wherein the level shift transistor is configured to receive an input referenced to a ground at the gate terminal and to generate an output at the drain terminal, wherein the output is referenced to a floating voltage; and

a resistive element between the source and the ground.

20. The level shift circuit of claim 19, wherein the gate is configured to receive a pulsed input signal, and wherein a duration of the pulsed input signal is less than 100 nanoseconds.

21. A level shift circuit comprising:

a GaN-based level shift transistor, comprising;

a gate connected to a gate terminal,

a drain connected to a drain terminal, and

a source connected to a source terminal,

wherein the level shift transistor is configured to receive an input referenced to a ground at the gate terminal and to generate an output at the drain terminal, wherein the output is referenced to a floating voltage; and

a bond pad,

wherein the drain of the level shift transistor is less than 100 microns from the bond pad.

22. The level shift circuit of claim 21, wherein the level shift transistor includes a source ohmic contact area connected to the source terminal, wherein the source terminal is connected to the bond pad, and wherein the bond pad is more than 100 times the source ohmic contact area.

23. The level shift circuit of claim 21, wherein the level shift transistor includes a drain ohmic contact area connected to the drain terminal, wherein the drain terminal is connected to the bond pad, and wherein the bond pad is more than 100 times the drain ohmic contact area.