Half bridge driver circuits

• US 9,571,093 B2
• Filed: 10/07/2015
• Issued: 02/14/2017
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel M., Sharma, Santosh, Zhang, Ju Jason
• Primary Examiner(s): Dole, Timothy J
• Assistant Examiner(s): Tiku, Sisay G
• Application Number:
  US14/877,574
• Publication Number:
  US 20160079975A1
• Time in Patent Office: 496 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 2217/0063 High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 2217/0072 Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments, a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions.

Claims

1. A half bridge GaN circuit, comprising:

a low side circuit, comprising;

a low side switch having a low side switch control gate and a first source,

a low side switch driver, comprising;

a first low side switch driver input configured to receive a first logic signal, wherein the first logic signal is referenced to a voltage at the first source,

a second low side switch driver input configured to receive a low side switch driver control signal,

a first low side switch driver output connected to the low side switch control gate,

a second low side switch driver output configured to transmit a level shift driver control signal, and

a third low side switch driver output configured to transmit a second level shift input signal,

a level shift driver, comprising;

a first level shift driver input connected to a second logic signal, wherein the second logic signal is referenced to the voltage of the first source,

a second level shift driver input configured to receive the level shift driver control signal from the second low side switch driver output,

a first level shift driver output, configured to transmit the low side switch driver control signal to the second low side switch driver input, and

a second level shift driver output, configured to transmit a first level shift input signal,

a first level shift circuit configured to receive the first level shift input signal and to generate a first level shift signal, and

a second level shift circuit configured to receive the second level shift input signal and to generate a second level shift signal; and

a high side circuit, comprising;

a high side switch having a high side switch control gate and a second source,

a first high side receiver circuit referenced to a voltage at the second source and configured to receive the first level shift signal and to generate a first high side driver control signal,

a second high side receiver circuit referenced to the voltage of the second source and configured to receive the second level shift signal and to generate a second high side driver control signal, and

a high side switch driver referenced to the voltage of the second source, wherein the high side switch driver comprises;

one or more logic inputs configured to receive the first and second high side driver control signals, and

a high side switch driver output connected to the high side switch control gate,

wherein the first and second high side receiver circuits are configured to prevent a change of voltage state of the high side control gate in response to voltage transients of the voltage of the second source.

2. The half bridge GaN circuit of claim 1, wherein the first level shift signal is configured to control turn-off of the high side switch, and wherein the first level shift signal is further configured to prevent turn-on of the high side control gate in response to the voltage transients of the voltage of the second source.

3. The half bridge GaN circuit of claim 1, wherein the second level shift circuit is coupled with the second high side receiver circuit, wherein the second high side receiver circuit is configured to generate a first pulse signal referenced to the voltage of the second source, and wherein the first pulse signal is synchronous with the voltage transients of the voltage of the second source.

4. The half bridge GaN circuit of claim 3, wherein the first level shifter is coupled with the first high side receiver circuit, wherein the first pulse signal is transmitted to the gate of an enhancement mode transistor configured to pull up the output of the voltage of the first level shift signal.

5. The half bridge GaN circuit of claim 4, wherein the second receiver circuit is configured to generate a second pulse signal, wherein the second pulse signal is synchronous with the voltage transients of the voltage of the second source, and wherein the first receiver circuit is configured to receive the second pulse signal, and, in response to the second pulse signal, to prevent turn-on of the high side control gate.

6. The half bridge GaN circuit of claim 4, wherein the second receiver circuit is configured to generate a second pulse signal, wherein the second pulse signal is synchronous with the voltage transients of the voltage of the second source, and wherein the high side switch driver is configured to receive the second pulse signal, and, in response to the second pulse signal, to prevent turn-on of the high side switch control gate.

7. The half bridge GaN circuit of claim 4, wherein the first receiver circuit is configured to generate a second pulse signal, wherein the second pulse signal is synchronous with the voltage transients of the voltage of the second source, and wherein the second receiver circuit is configured to receive the second pulse signal, and, in response to the second pulse signal, to prevent turn-off of the high side switch control gate.

8. The half bridge GaN circuit of claim 3, wherein the first level shift circuit is configured to generate a pulse in response to a high to low transition of the second logic signal and to output the pulse as the first level shift signal, wherein, in response to the first level shift signal, the first high side receiver is configured to reduce a turn-off propagation delay of the high side control gate.

9. The half bridge GaN circuit of claim 1, wherein the first level shift circuit is configured to limit the turn-on duration of the high side switch.

10. The half bridge GaN circuit of claim 1, wherein the level shift driver comprises a first pulse generator configured to generate a pulse in response to a high to low transition of the second logic signal and to transmit the pulse to the first level shift driver output as the low side switch driver control signal.

11. The half bridge GaN circuit of claim 10, wherein the low side switch control gate is controlled according to a logical combination of the low side switch driver control signal, the first logic signal, and the second logic signal.

12. The half bridge GaN circuit of claim 1, wherein the low side switch driver comprises a second pulse generator configured to generate a pulse in response to a high to low transition of the first logic signal and to transmit the pulse to the first level shift driver output as the low side switch driver control signal.

13. The half bridge GaN circuit of claim 12, wherein the high side switch control gate is controlled according to a logical combination of the low side switch driver control signal, the first logic signal, and the second logic signal.

14. A half bridge GaN circuit, comprising:

a low side circuit, comprising;

a low side switch having a low side switch control gate and a first source,

a low side switch driver, comprising;

a first low side switch driver input configured to receive a first logic signal, wherein the first logic signal is referenced to a voltage at the first source,

a second low side switch driver input configured to receive a low side switch driver control signal,

a first low side switch driver output connected to the low side switch control gate,

a second low side switch driver output configured to transmit a level shift driver control signal, and

a third low side switch driver output configured to transmit a second level shift input signal,

a level shift driver, comprising;

a first level shift driver input connected to a second logic signal, wherein the second logic signal is referenced to the voltage of the first source,

a second level shift driver input configured to receive the level shift driver control signal from the second low side switch driver output,

a first level shift driver output, configured to transmit the low side switch driver control signal to the second low side switch driver input, and

a second level shift driver output, configured to transmit a first level shift input signal,

a first level shift circuit configured to receive the first level shift input signal and to generate a first level shift signal, and

a second level shift circuit configured to receive the second level shift input signal and to generate a second level shift signal; and

a high side circuit, comprising;

a high side switch having a high side switch control gate and a second source,

a first high side receiver circuit referenced to a voltage at the second source and configured to receive the first level shift signal and to generate a first high side driver control signal,

a second high side receiver circuit referenced to the voltage of the second source and configured to receive the second level shift signal and to generate a second high side driver control signal, and

a high side switch driver referenced to the voltage of the second source, wherein the high side switch driver comprises;

one or more logic inputs configured to receive the first and second high side driver control signals, and

a high side switch driver output connected to the high side switch control gate,

wherein the first and second level shift signals comprise a plurality of pulses, and

wherein the high side switch driver is configured to transmit a high side switch gate control signal based on the pulses to the high side switch control gate, wherein durations of on and off times of the high side switch are based on durations of the pulses.

15. The half bridge GaN circuit of claim 14, wherein the high side circuit further comprises:

an enhancement mode transistor configured to pull up the voltage of one or more of the first and second level shift signals;

a state storage element; and

a trigger circuit coupled to the enhancement mode transistor, wherein the trigger circuit is configured to detect a change in state of the state storage element, and to cause the enhancement mode transistor to pull up the voltage of one or more of the first and second level shift signals.

16. A half bridge GaN circuit, comprising:

a low side circuit, comprising;

a low side switch having a low side switch control gate and a first source,

a low side switch driver, comprising;

a first low side switch driver input configured to receive a first logic signal, wherein the first logic signal is referenced to a voltage at the first source,

a second low side switch driver input configured to receive a low side switch driver control signal,

a first low side switch driver output connected to the low side switch control gate,

a second low side switch driver output configured to transmit a level shift driver control signal, and

a third low side switch driver output configured to transmit a second level shift input signal,

a level shift driver, comprising;

a first level shift driver input connected to a second logic signal, wherein the second logic signal is referenced to the voltage of the first source,

a second level shift driver input configured to receive the level shift driver control signal from the second low side switch driver output,

a first level shift driver output, configured to transmit the low side switch driver control signal to the second low side switch driver input, and

a second level shift driver output, configured to transmit a first level shift input signal,

a first level shift circuit configured to receive the first level shift input signal and to generate a first level shift signal, and

a second level shift circuit configured to receive the second level shift input signal and to generate a second level shift signal; and

a high side circuit, comprising;

a high side switch having a high side switch control gate and a second source,

a first high side receiver circuit referenced to a voltage at the second source and configured to receive the first level shift signal and to generate a first high side driver control signal,

a second high side receiver circuit referenced to the voltage of the second source and configured to receive the second level shift signal and to generate a second high side driver control signal,

a high side switch driver referenced to the voltage of the second source, wherein the high side switch driver comprises;

one or more logic inputs configured to receive the first and second high side driver control signals, and

a high side switch driver output connected to the high side switch control gate, and

a trigger circuit configured to, in response to a voltage of a first power supply referenced to the voltage of the second source being less than a threshold greater than the voltage of the second source, cause the high side switch to turn-off.

17. The half bridge GaN circuit of claim 16, wherein the trigger circuit comprises a hysteretic inverter coupled to the first power supply, wherein the hysteretic inverter is configured to, in response to the voltage of the first power supply being less than the threshold greater than the voltage of the second source, cause the high side switch to turn-off.

18. The half bridge GaN circuit of claim 16, wherein the high side circuit further comprises a state storage element, wherein the state storage element is configured to, in response to the voltage of the first power supply being less than the threshold greater than the voltage of the second source, cause the trigger circuit to turn off the high side switch.

19. The half bridge GaN circuit of claim 18, wherein the state storage element is configured to prevent the high side switch from turning on until after a low to high transition of the second logic signal.