Low power high resolution oscillator based voltage sensor

• US 9,575,095 B2
• Filed: 08/13/2014
• Issued: 02/21/2017
• Est. Priority Date: 08/13/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Zhang, Junmou, Zhang, Chuang, Pan, Yuancheng Christopher, Chen, Nan
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US14/459,208
• Publication Number:
  US 20160047847A1
• Time in Patent Office: 923 Days
• US Class Current: 1/1
• CPC Class Codes: G01R 19/0084 measuring voltage only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G01R 19/16552 in I.C. power supplies
• CPC Class Codes: G01R 23/02 Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
• CPC Class Codes: G01R 31/282 Testing of electronic circuits specially adapted for particular applications not provided for elsewhere G01R31/2801 and G01R31/2851 take precedence

Abstract

Systems and methods for sensing voltage on a chip are described herein. In one embodiment, a voltage sensor comprises a voltage-controlled oscillator coupled to a voltage being sensed, and a plurality of transition detectors, wherein each of the transition detectors is coupled to a different location on the oscillator, and wherein each of the transition detectors is configured to count a number of transitions at the respective location over a time period. The voltage sensor also comprises an adder configured to add the numbers of transitions from the transition detectors to generate an output value that is approximately proportional to the voltage.

Claims

1. A voltage sensor, comprising:

a voltage-controlled oscillator coupled to a voltage being sensed;

a plurality of transition detectors, wherein each of the transition detectors is coupled to a different location on the oscillator, and wherein each of the transition detectors is configured to count a number of transitions at the respective location over a time period; and

an adder configured to add the numbers of transitions from the transition detectors to generate an output value that is approximately proportional to the voltage.

2. The voltage sensor of claim 1, wherein the oscillator comprises a plurality of inverters coupled into a loop, each of the inverters is biased by the voltage, and each of the transition detectors is coupled to an output of a different one of the inverters.

3. The voltage sensor of claim 2, wherein each of the transition detectors is configured to count transitions corresponding to rising edges at the respective location.

4. The voltage sensor of claim 2, wherein each of the transition detectors is configured to count transitions corresponding to rising edges and falling edges at the respective location.

5. The voltage sensor of claim 1, wherein each of the transition detectors is configured to receive a clock signal, and the time period comprises a cycle of the clock signal.

6. The voltage sensor of claim 5, wherein each of the transition detectors comprises:

a counter configured to count transitions at the respective location on the oscillator, and to output a count of the transitions;

a first latch configured to latch a current count from the counter on a current edge of the clock signal;

a second latch configured to latch a previous count that was latched by the first latch from the counter on a previous edge of the clock signal; and

a subtractor configured to compute a difference between the current count latched by the first latch and the previous count latched by the second latch.

7. The voltage sensor of claim 6, wherein the counter in each transition detector is configured to count transitions corresponding to rising edges at the respective location on the oscillator.

8. The voltage sensor of claim 6, wherein the counter in each transition detector is configured to count transitions corresponding to rising edges and falling edges at the respective location on the oscillator.

9. The voltage sensor of claim 5, wherein each of the transition detectors comprises:

a first latch configured to latch a current logic state at the respective location on the oscillator on a current edge of the clock signal;

a second latch configured to latch a previous logic state at the respective location on the oscillator, wherein the previous logic state was latched by the first latch on a previous edge of the clock signal; and

an XOR gate configured to output a logic one if the current and previous logic states are different, the logic one being indicative of one detected transition at the respective location.

10. The voltage sensor of claim 1, wherein the voltage is a voltage of a power supply rail.

11. The voltage sensor of claim 1, wherein each of the transition detectors comprises a counter configured to count transitions at the respective location on the oscillator.

12. The voltage sensor of claim 11, wherein the counter is a multiple bit counter.

13. A method for sensing a voltage, comprising:

inputting the voltage to a voltage-controlled oscillator;

counting a number of transitions at each one of a plurality of different locations on the oscillator over a time period; and

adding the numbers of transitions for the different locations to generate an output value that is approximately proportional to the voltage.

14. The method of claim 13, wherein the oscillator comprises a plurality of inverters coupled into a loop, each of the inverters is biased by the voltage, and each of the locations corresponds to an output of a different one of the inverters.

15. The method of claim 13, wherein counting the number of transitions at each location comprises detecting rising edges at each location.

16. The method of claim 13, wherein counting the number of transitions at each location comprises detecting rising edges and falling edges at each location.

17. The method of claim 13, further comprising receiving a clock signal, wherein the time period comprises a cycle of the clock signal.

18. The method of claim 13, wherein the counting of the number of transitions at each one of the plurality of different locations on the oscillator is performed by a plurality of transition detectors each including a counter configured to count transitions at the respective location on the oscillator.

19. The method of claim 18, wherein the counter is a multiple bit counter.

20. An apparatus for sensing a voltage, comprising:

means for inputting the voltage to a voltage-controlled oscillator;

means for counting a number of transitions at each one of a plurality of different locations on the oscillator over a time period; and

means for adding the numbers of transitions for the different locations to generate an output value that is approximately proportional to the voltage.

21. The apparatus of claim 20, wherein the oscillator comprises a plurality of inverters coupled into a loop, each of the inverters is biased by the voltage, and each of the locations corresponds to an output of a different one of the inverters.

22. The apparatus of claim 20, wherein the means for counting the number of transitions at each location comprises means for detecting rising edges at each location.

23. The apparatus of claim 20, wherein the means for counting the number of transitions at each location comprises means for detecting rising edges and falling edges at each location.

24. The apparatus of claim 20, further comprising means for receiving a clock signal, wherein the time period comprises a cycle of the clock signal.

25. The apparatus of claim 20, wherein the means for counting a number of transitions includes a plurality of transition detectors wherein each of the transition detectors comprises a counter configured to count transitions at the respective location on the voltage-controlled oscillator.

26. The apparatus of claim 25, wherein the counter is a multiple bit counter.

27. A system, comprising:

a voltage sensor, the voltage sensor comprising;

a voltage-controlled oscillator coupled to a voltage being sensed;

a plurality of transition detectors, wherein each of the transition detectors is coupled to a different location on the oscillator, and wherein each of the transition detectors is configured to count a number of transitions at the respective location over a time period; and

an adder configured to add the numbers of transitions from the transition detectors to generate an output value that is approximately proportional to the voltage; and

a voltage management device configured to estimate the voltage based on the output value, and to adjust an operating frequency of a circuit based on the estimated voltage.

28. The system of claim 27, wherein the voltage management device is configured to compare the estimated voltage with a voltage threshold, and to reduce the operating frequency of the circuit if the estimated voltage is below the voltage threshold.

29. The system of claim 28, wherein each of the transition detectors is configured to receive a clock signal, and the time period comprises a cycle of the clock signal.

30. The system of claim 28, wherein the voltage is a voltage of a power supply rail, and the circuit is coupled to the power supply rail.

31. The system of claim 27, wherein the oscillator comprises a plurality of inverters coupled into a loop, each of the inverters is biased by the voltage, and each of the transition detectors is coupled to an output of a different one of the inverters.

32. The system of claim 31, wherein each of the transition detectors is configured to count transitions corresponding to rising edges at the respective location.

33. The system of claim 31, wherein each of the transition detectors is configured to count transitions corresponding to rising edges and falling edges at the respective location.

34. The system of claim 27, wherein each of the transition detectors comprises a counter configured to count transitions at the respective location on the oscillator.

35. The system of claim 34, wherein the counter is a multiple bit counter.