Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping
First Claim
1. A method of measuring a delay of an edge of a first signal with respect to an edge of a second signal within an integrated circuit, the method comprising:
- controlling a frequency of a clock signal of the integrated circuit from which the first signal and the second signal are synchronously derived;
within the integrated circuit, first propagating the edge of the first signal through a tapped delay line;
within the integrated circuit, first capturing first tap positions of the edge of the first signal over multiple first measurements;
first computing a first average of the first tap positions of the edge of the first signal, wherein the controlling controls the frequency of the clock signal to determine a first frequency for which the first average of the first tap positions lies at a boundary between a pair of adjacent tap positions of the tapped delay line;
within the integrated circuit, second propagating an edge of the second signal through the tapped delay line;
within the integrated circuit, second capturing second tap positions of the edge of the second signal over multiple second measurements;
second computing an average of the second tap positions of the edge of the second signal, wherein the controlling controls the frequency of the clock signal to determine a second frequency for which the second average of the second tap positions lies at the boundary between the pair of adjacent tap positions of the tapped delay line; and
computing the delay as a difference between the periods of the first frequency and the second frequency.
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Accused Products
Abstract
A delay measurement technique using a tapped delay line edge capture circuit that captures tap position of edges within the delay line provides accuracy of measurement to one pico-second and below. A control circuit causes latches to capture an edge of a signal delayed through the delay line at taps of the delay line. The frequency of a clock from which the signal is derived is adjusted and tap outputs are captured by latches and averaged. A first frequency is found at which the average edge position is midway between two adjacent tap positions. A second signal, which may be the reference signal that clocks the latches, is propagated through the delay line and a second frequency is found for which the average edge position lies at the boundary between the two tap positions. The delay is determined from the difference between the periods of the first frequency and the second frequency.
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Citations
7 Claims
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1. A method of measuring a delay of an edge of a first signal with respect to an edge of a second signal within an integrated circuit, the method comprising:
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controlling a frequency of a clock signal of the integrated circuit from which the first signal and the second signal are synchronously derived; within the integrated circuit, first propagating the edge of the first signal through a tapped delay line; within the integrated circuit, first capturing first tap positions of the edge of the first signal over multiple first measurements; first computing a first average of the first tap positions of the edge of the first signal, wherein the controlling controls the frequency of the clock signal to determine a first frequency for which the first average of the first tap positions lies at a boundary between a pair of adjacent tap positions of the tapped delay line; within the integrated circuit, second propagating an edge of the second signal through the tapped delay line; within the integrated circuit, second capturing second tap positions of the edge of the second signal over multiple second measurements; second computing an average of the second tap positions of the edge of the second signal, wherein the controlling controls the frequency of the clock signal to determine a second frequency for which the second average of the second tap positions lies at the boundary between the pair of adjacent tap positions of the tapped delay line; and computing the delay as a difference between the periods of the first frequency and the second frequency. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification