Graphics display system with unified memory architecture

• US 9,575,665 B2
• Filed: 07/02/2015
• Issued: 02/21/2017
• Est. Priority Date: 11/09/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Tang, Chengfuh, Xie, Xiaodong, Patterson, James T., Kranawetter, Greg A.
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Hassan, Aurangzeb
• Application Number:
  US14/790,923
• Publication Number:
  US 20150317085A1
• Time in Patent Office: 600 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 9/00 Image coding bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 : characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 : using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 : Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/59 : involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/440263 : by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/04 : Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0122 : the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers

Abstract

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Claims

1. A memory system comprising:

a memory that is shared by a plurality of devices;

a first memory controller;

a second memory controller;

a memory request arbiter coupled to the memory, wherein the memory request arbiter is configured to perform real time scheduling of memory requests from different devices having different priorities and provides access to the memory by the plurality of devices, the memory request arbiter comprising a first arbiter coupled to the first memory controller and a second arbiter coupled to the second memory controller; and

a memory select circuit configured to;

receive the memory requests from the plurality of devices; and

for each of the memory requests, select one of the first arbiter or the second arbiter using a characteristic of the memory request and provide the memory request to the selected one of the first arbiter or the second arbiter;

a circuit component associated with one or more of the plurality of devices and coupled between the associated devices and the memory request arbiter, wherein the circuit component is configured to enforce a minimum interval between subsequent accesses by the associated device to the memory, the minimum interval configured to prevent a first device of the plurality of devices from accessing the memory during consecutive memory cycles when a second device of the plurality of devices is also requesting access to the memory.

2. The memory system of claim 1, wherein one or more of the plurality of devices is sensitive to latency and does not have determinable periodic behavior.

3. The memory system of claim 1, wherein the one or more devices associated with the circuit component include a central processing unit.

4. The memory system of claim 1, wherein the one or more devices associated with the circuit component make high priority service requests to access the memory through the circuit component.

5. The memory system of claim 1, further comprising a round robin server for handling low priority tasks.

6. The memory system of claim 1, wherein the characteristic of the memory request comprises an address of the memory request.

7. The memory system of claim 1, wherein the circuit component is a block out timer, the block out timer having a period programmable for system tuning.

8. A method comprising:

receiving a plurality of memory requests from a plurality of devices for access to a memory shared by the plurality of devices, the plurality of memory requests having different priorities;

for each of the memory requests, selecting one of a first arbiter or a second arbiter using a characteristic of the memory request;

for each of the memory requests, providing the memory request to the selected one of the first arbiter or the second arbiter;

performing scheduling of the memory requests using the first arbiter and the second arbiter; and

enforcing a minimum interval between accesses of the memory, the minimum interval configured to prevent a first device of the plurality of devices from accessing the memory during consecutive memory cycles when a second device of the plurality of devices is also requesting access to the memory, wherein a circuit component associated with one or more of the plurality of devices is coupled between the associated devices and the memory request arbiter, wherein the circuit component is configured to enforce the minimum interval between subsequent accesses by the associated device to the memory.

9. The method of claim 8, wherein performing scheduling of the memory requests comprises providing access to the memory by one or more of the plurality of devices sensitive to latency and not having determinable periodic behavior.

10. The method of claim 8, wherein the one or more devices associated with the circuit component include a central processing unit.

11. The method of claim 8, wherein the one or more devices associated with the circuit component make high priority service requests to access the memory through the circuit component.

12. The method of claim 8, further comprising handling low priority tasks using a round robin server.

13. The method of claim 8, wherein the characteristic of the memory request comprises an address of the memory request.

14. The memory system of claim 8, wherein the circuit component is a block out timer, the block out timer having a period programmable for system tuning.

15. A memory system comprising:

circuitry configured to;

receive a plurality of memory requests from a plurality of devices for access to a memory shared by the plurality of devices, the plurality of memory requests having different priorities;

for each of the memory requests, select one of a first arbiter or a second arbiter using a characteristic of the memory request, the first arbiter and the second arbiter implemented within the circuitry;

for each of the memory requests, provide the memory request to the selected one of the first arbiter or the second arbiter;

perform scheduling of the memory requests using the first arbiter and the second arbiter; and

enforce a minimum interval between accesses of the memory, the minimum interval configured to prevent a first device of the plurality of devices from accessing the memory during consecutive memory cycles when a second device of the plurality of devices is also requesting access to the memory, wherein the circuitry comprises a circuit component associated with one or more of the plurality of devices and coupled between the associated devices and the memory request arbiter, wherein the circuit component is configured to enforce the minimum interval between subsequent accesses by the associated device to the memory.

16. The memory system of claim 15, wherein one or more of the plurality of devices is sensitive to latency and does not have determinable periodic behavior.

17. The memory system of claim 15, wherein the one or more devices associated with the circuit component include a central processing unit.

18. The memory system of claim 15, wherein the one or more devices associated with the circuit component make high priority service requests to access the memory through the circuit component.

19. The memory system of claim 15, wherein the characteristic of the memory request comprises an address of the memory request.

20. The memory system of claim 15, wherein the circuit component is a block out timer, the block out timer having a period programmable for system tuning.