Loading boot code from multiple memories

• US 9,575,768 B1
• Filed: 01/03/2014
• Issued: 02/21/2017
• Est. Priority Date: 01/08/2013
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Kim, Myungque
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Chang, Eric
• Application Number:
  US14/147,087
• Time in Patent Office: 1,145 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

The present disclosure describes apparatuses and techniques for loading boot code from multiple memories. In some aspects a transfer operation transferring a portion of boot code from a memory of a first type is initiated prior to completion of another transfer operation transferring another portion of the boot code from another memory of the first type. This can be effective to enable concurrent transfers of boot code from multiple memories of the first type into a memory of a second type for execution. By so doing, a speed at which boot code is transferred into the memory of the second type is increased, which may result in decreased device boot times.

Claims

1. A method comprising:

initiating, via a direct memory access (DMA) controller, a first transfer operation transferring a first portion of boot code from a first non-volatile memory of a device into a volatile memory of the device, the first portion of boot code including a first signature that indicates a presence of the first portion of boot code in the first non-volatile memory;

initiating, via the DMA controller and prior to completion of the first transfer operation, a second transfer operation that concurrently transfers a second portion of the boot code from a second non-volatile memory of the device into the volatile memory of the device, the second portion of boot code including a second signature that indicates a presence of the second portion of boot code in the second non-volatile memory; and

causing, after completion of at least the first transfer operation of the first portion of boot code, a processor of the device to execute of the first and second portions of the boot code from the volatile memory of the device effective to initiate boot operations of the device.

2. The method of claim 1, wherein initiating the first and second transfer operations comprises configuring the DMA controller to transfer the first portion of the boot code from the first non-volatile memory and transfer the second portion of the boot code from the second non-volatile memory, respectively.

3. The method of claim 1 further comprising selecting, from two or more non-volatile memories, the first and second non-volatile memories from which to transfer the boot code into the volatile memory.

4. The method of claim 3, wherein selecting the first and second non-volatile memories from the two or more non-volatile memories comprises determining, based on the first and second signatures, that the first and second non-volatile memories include the first and second portions of boot code.

5. The method of claim 1, wherein a data-transfer speed of the first transfer operation is different from a data-transfer speed of the second transfer operation.

6. The method of claim 1, wherein the first portion of boot code and the second portion of boot code are respective portions of a composite boot image that, responsive to execution, implements the boot operations of the device.

7. The method of claim 1, wherein the first non-volatile memory or the second non-volatile memory comprises one of a serial peripheral interface (SPI) Flash memory, electronically-erasable programmable read-only memory (EEPROM), NAND Flash, embedded Flash, or embedded multimedia card (eMMC) device.

8. One or more hardware-based computer-readable memory devices storing processor-executable instructions that, responsive to execution by a processor of a device, implement a boot manager to:

initiate, via a direct memory access (DMA) controller, a first transfer operation transferring a first portion of boot code from a first non-volatile memory of the device into a volatile memory of the device, the first portion of boot code including a first signature that indicates a presence of the first portion of boot code in the first non-volatile memory;

initiate, via the DMA controller and prior to completion of the first transfer operation, a second transfer operation that concurrently transfers a second portion of the boot code from a second non-volatile memory of the device into the volatile memory of the device, the second portion of the boot code including a second signature that indicates a presence of the second portion of the boot code in the second non-volatile memory; and

execute, via the processor and after completion of at least the first transfer operation of the first portion of boot code, the first and second portions of the boot code from the volatile memory of the device.

9. The one or more hardware-based computer-readable memory devices of claim 8, wherein the boot manager is further implemented to initiate the first transfer operation or the second transfer operation in response to respectively determining, based on the first signature or the second signature, that the first non-volatile memory includes the first portion of the boot code or the second non-volatile memory includes the second portion of the boot code.

10. The one or more hardware-based computer-readable memory devices of claim 8, wherein a data-transfer speed of the first non-volatile memory is different from a data-transfer speed of the second non-volatile memory.

11. The one or more hardware-based computer-readable memory devices of claim 10, wherein a size of the first portion of boot code is different from a size of the second portion of boot code, and a larger of the two portions of boot code is stored in the non-volatile memory having a higher of the two data-transfer speeds.

12. The one or more hardware-based computer-readable memory devices of claim 8, wherein the first and second portions of the boot code are interleaved portions of a composite boot image formed by the boot code, the first and second portions of boot code interleaved on a per-byte, per-page, or per-block basis.

13. The one or more hardware-based computer-readable memory devices of claim 8, wherein the first non-volatile memory or the second non-volatile memory comprise one of a serial peripheral interface (SPI) Flash memory, electronically-erasable programmable read-only memory (EEPROM), NAND Flash, embedded Flash, or embedded multimedia card (eMMC) device.

14. A System-on-Chip comprising:

a processor configured to execute code to boot and implement functionalities of a device;

volatile memory from which boot code is executable by the processor;

a memory controller configured to enable concurrent access of multiple non-volatile memories; and

a boot manager configured to;

determine, based on signatures within the boot code, which of the multiple non-volatile memories include a respective portion of boot code;

initiate, via the memory controller, a direct memory access (DMA) transfer operation transferring one of the respective portions of boot code from one of the multiple non-volatile memories into the volatile memory;

initiate, via the memory controller and prior to completion of the transfer operation, at least one other DMA transfer operation that simultaneously transfers another respective portion of the boot code from another of the multiple non-volatile memories into the volatile memory; and

causing, responsive to completion of at least one of the DMA transfer operations, the processor to initiate execution of the respective portions of the boot code from the volatile memory.

15. The System-on-Chip of claim 14, wherein the multiple non-volatile memories are external non-volatile memories associated with the System-on-Chip via multiple respective memory interfaces.

16. The System-on-Chip of claim 15, wherein a data-transfer speed of the DMA transfer operation is different from a data-transfer speed of the other DMA transfer operation.

17. The System-on-Chip of claim 15, wherein the memory controller includes or is implemented as a DMA controller to implement the DMA transfer operation and the other DMA transfer operation.

18. The System-on-Chip of claim 14, wherein the boot manager is further configured to initiate, prior to completion of the transfer operation, at least two other DMA transfer operations that simultaneously transfer two other portions of the boot code from respective ones of the multiple non-volatile memories, the respective portion and at least two other respective portions of the boot code being transferred into the volatile memory via a system bus or memory bus of the System-on-Chip.

19. The System-on-Chip of claim 14, wherein a size of the respective portion of boot code is different from a size of the other respective portion of boot code.

20. The System-on-Chip of claim 14, wherein the non-volatile memory and the other non-volatile memory are different types of non-volatile memory.