Display panel with alternating sub-pixel electrodes

• US 9,576,547 B2
• Filed: 11/11/2014
• Issued: 02/21/2017
• Est. Priority Date: 12/24/2008
• Status: Expired due to Fees

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Jung, Kwang-Chul, Chai, Chong-Chul, Jung, Mee-Hye
• Primary Examiner(s): Snyder, Adam J
• Application Number:
  US14/538,589
• Publication Number:
  US 20150061987A1
• Time in Patent Office: 833 Days
• Field of Search: 345/87, 345/695
• US Class Current: 1/1
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 2201/124 interdigital
• CPC Class Codes: G09G 2300/0434 Flat panel display in which a field is applied parallel to the display plane
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 2320/0219 Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

A display panel includes a first sub-pixel electrode and a second sub-pixel electrode alternating with each other to form a horizontal electric field, a first data line transmitting a first data voltage to the first sub-pixel electrode, and a second data line transmitting a second data voltage to the second sub-pixel electrode, wherein the second sub-pixel electrode is formed to overlap the first and second data lines.

Claims

1. A display panel comprising:

a plurality of gate lines disposed on a substrate that extend in a first direction;

a plurality of first data lines that extend in a second direction, crossing the plurality of gate lines and transmitting a first data voltage;

a plurality of second data lines parallel with the plurality of first data lines and transmitting a second data voltage; and

a plurality of pixels defined by the plurality of gate lines and the plurality of first data lines, each of the plurality of pixels including first and second sub-pixel electrodes alternating with each other to form a horizontal electric field,

wherein the second sub-pixel electrode is formed along the first and second data lines and the gate line of a previous first sub-pixel electrode,

wherein the second sub-pixel electrode overlaps the first and second data lines without crossing the first and second data lines,

wherein the first sub-pixel electrode does not overlap the first and second data lines and the second sub-pixel electrode,

wherein an overlap area between the second sub-pixel electrode and the first data line is the same as that between the second sub-pixel electrode and the second data line,

wherein the first sub-pixel electrode includes first stripes that extend in a third direction, first stripes that extend in a fourth direction, and a first connecting portion that connects the first stripes extending in the third direction and the first stripes extending in the fourth direction, and

wherein the second sub-pixel electrode includes second stripes that extend in the third direction, second stripes that extend in the fourth direction, and a second connecting portion that connects the second stripes extending in the third direction and the second stripes extending in the fourth direction, and

wherein the third direction is different from the first direction, the second direction and the fourth direction.

2. The display panel of claim 1, wherein an absolute value of the first data voltage is the same as that of the second data voltage,

the first data voltage has a first polarity, and

the second data voltage has a second polarity different from the first polarity.

3. The display panel of claim 2, wherein

the first data voltage has polarities repeatedly alternating between the first polarity and the second polarity different from the first polarity for every first data line of each pixel,

the second data voltage has polarities repeatedly alternating between the second polarity and the first polarity for every second data line of each pixel, and

when the first data voltage applied to the first data line of each pixel has the first polarity, the second data voltage applied to the second data line has the second polarity.

4. The display panel of claim 1, wherein

the plurality of pixels includes a first pixel and a second pixel adjacent to each other in a direction of the gate lines,

the second sub-pixel electrode of the first pixel is connected to the first data line of the first pixel, and

the second sub-pixel electrode of the second pixel is connected to the second data line of the second pixel.

5. The display panel of claim 1, further comprising

a first parasitic capacitor between each of the second sub-pixel electrodes and each of the first data lines,

a second parasitic capacitor between each of the second sub-pixel electrodes and each of the second data lines,

wherein a capacitance of the first parasitic capacitor is the same as that of the second parasitic capacitor.

6. A display panel comprising:

a gate line that extends in the first direction and transmitting a gate voltage;

first and second sub-pixel electrodes alternating with each other to form a horizontal electric field,

a first switching device selectively connecting the first sub-pixel electrode and a first data line according to the gate voltage;

a second switching device selectively connecting the second sub-pixel electrode and a second data line according to the gate voltage; and

a liquid crystal capacitor formed between the first and second sub-pixel electrodes,

wherein the first data line and the second data lines extend in a second direction,

wherein when the first and second switching devices are turned off and polarities of first and second data voltages applied to the first and second data lines are changed, there is no voltage variation between the first and second sub-pixel electrodes,

wherein the second sub-pixel electrode overlaps the first and second data lines without crossing the first and second data lines,

wherein the first sub-pixel electrode does not overlap the first and second data lines and the second sub-pixel electrode, and

wherein an overlap area between the second sub-pixel electrode and the first data line is the same as that between the second sub-pixel electrode and the second data line,

wherein the first sub-pixel electrode includes first stripes that extend in a third direction, first stripes that extend in a fourth direction, and a first connection portion that connects the first stripes extend ing in the third direction and the first stripes extending in the fourth direction, and

wherein the second sub-pixel electrode includes second stripes that extend in the third direction, second stripes that extend in the fourth direction, and a second connecting portion that connects the second stripes extending in the third direction and the second stripes extending in the fourth direction, and

wherein the third direction is different from the first direction, the second direction and the fourth direction.

7. The display panel of claim 6, further comprising

a first parasitic capacitor between each of the second sub-pixel electrodes and each of the first data lines,

a second parasitic capacitor between each of the second sub-pixel electrodes and each of the second data lines,

wherein a capacitance of the first parasitic capacitor is the same as that of a second parasitic capacitor.

8. The display panel of claim 6, wherein

the first sub-pixel electrode includes first stripes, and first connecting portions connecting the first stripes, and

the second sub-pixel electrode includes second stripes parallel with the first stripes, and second connecting portions connecting the second stripes.

9. The display panel of claim 8, wherein the second connecting portions partially overlap the first and second data lines along the first and second data lines.

10. The display panel of claim 6, wherein an absolute value of the first data voltage is the same as that of the second data voltage,

the first data voltage has a first polarity, and

the second data voltage has a second polarity different from the first polarity.