Nonvolatile memory device

• US 9,576,612 B2
• Filed: 12/22/2014
• Issued: 02/21/2017
• Est. Priority Date: 04/07/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Ansoo, Kim, In-Mo, Hwang, Jung-Seok
• Primary Examiner(s): Norman, James G
• Application Number:
  US14/578,632
• Publication Number:
  US 20150287437A1
• Time in Patent Office: 792 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/2257 Word-line or row circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A nonvolatile memory device includes a first memory block connected to first word lines, a second memory block arranged in a direction perpendicular to the first memory block and is connected to second word lines, first pass transistors for enabling the first word lines, and second pass transistors for enabling the second word lines. The first and second pass transistors are arranged in a horizontal direction with respect to the first and second memory blocks.

Claims

1. A nonvolatile memory device comprising:

first word lines and second word lines;

a first memory block including first sets of memory cells and electrically connected to the first word lines, the memory cells of each first set being disposed at the same level in the device as one another and the first sets of memory cells being stacked vertically one atop another such that the first memory block contains a plurality of memory cells at each of a plurality of different levels arrayed in a vertical direction in the device;

a second memory block including second sets of memory cells and electrically connected to the second word lines, the second memory block adjacent the first memory block in a first horizontal direction, the memory cells of each second set being disposed at the same level in the device as one another and the second sets of memory cells being stacked vertically one atop another such that the second memory block also contains a plurality of memory cells at each of a plurality of levels in the device;

first pass transistors enabling a selection of the first word lines; and

second pass transistors enabling a selection of the second word lines,

wherein the first pass transistors and the second pass transistors are disposed beside the memory blocks and are arrayed two-dimensionally, in parallel rows, in a horizontal plane perpendicular to the vertical direction, each of the rows containing a plurality of respective ones of the pass transistors, the rows spaced apart from each other in the first horizontal direction, and each of the rows of the pass transistors extending in a second horizontal direction different from the first horizontal direction,

the memory cells of the first and second memory blocks are arrayed in parallel rows spaced from each other in the first horizontal direction, and each of the rows of memory cells containing a plurality of respective ones of the memory cells and extending in the second horizontal direction, and

each of the first pass transistors is located between each of the second pass transistors and the first memory block.

2. The nonvolatile memory device of claim 1, further comprising:

third pass transistors enabling a selection of the first word lines; and

fourth pass transistors enabling a selection of the second word lines, and

wherein the third pass transistors and the fourth pass transistors are disposed beside the memory blocks and are arrayed in parallel rows each extending in the second horizontal direction.

3. The nonvolatile memory device of claim 2, wherein the first pass transistors and the second pass transistors are disposed to one side of the memory blocks, and the third pass transistors and the fourth pass transistors are disposed on the opposite side of the memory blocks.

4. The nonvolatile memory device of claim 1, wherein the first and second memory blocks each have a dimension as measured in the first direction, and

a first pass circuit unit of the first pass transistors or a second pass circuit of the second pass transistors has a first dimension, as measured in the first direction, which is twice that of each of the first and second memory blocks.

5. The nonvolatile memory device of claim 4, wherein the first pass transistors or the second pass transistors are arrayed in columns each extending in the first direction and containing a plurality of said first pass transistors or second pass transistors.

6. A nonvolatile memory device comprising:

a plurality of word lines;

a group of memory blocks connected to the plurality of word lines, each of the memory blocks including sets of memory cells, the memory cells of each set being disposed at the same level in the device as one another and the sets of memory cells being stacked vertically one atop such that each of the memory blocks contains a plurality of memory cells at each of a plurality of different levels arrayed in a vertical direction in the device; and

a plurality of pass transistor units,

wherein each of the pass transistor units is disposed beside the group of memory blocks so as to face the group of memory blocks in a horizontal direction, and each of the pass transistor units comprises a plurality of pass transistors,

the pass transistors constituting the pass transistor units collectively are disposed in a two-dimensional array in a horizontal plane perpendicular to the vertical direction, and

the pass transistor units enable the memory blocks, respectively.

7. The nonvolatile memory device of claim 6, wherein the plurality of memory blocks include first, second, third and fourth memory blocks,

the plurality of word lines include first word lines connected to the first memory block, second word lines connected to the second memory block, third word lines connected to the third memory block, and fourth word lines connected to the fourth memory block,

the pass transistor units comprise first, second, third and fourth pass transistor units connected to the first, second, third and fourth word lines, respectively, and

the first, second and third pass transistor units are interposed between the fourth pass transistor unit and the group of memory blocks.

8. The nonvolatile memory device of claim 7, wherein the memory blocks are arrayed in a first direction, and

the first through third pass transistor units are arrayed in the first direction.

9. The nonvolatile memory device of claim 8, wherein each of the pass transistor units includes a plurality of respective ones of the pass transistors, and

in each of the pass transistor units, the pass transistors of are arrayed in columns each extending in the first direction.

10. The nonvolatile memory device of claim 7, wherein the pass transistor units further comprise fifth, sixth, seventh and eighth pass transistor units connected to the first, second, third and fourth word lines, respectively, and

the fifth, sixth and seventh pass transistor units are interposed between the eighth pass transistor unit and the group of memory blocks.

11. The nonvolatile memory device of claim 10, wherein the fifth, sixth, seventh and eighth pass transistor units are disposed on an opposite side of the group of memory blocks from the first, second, third and fourth pass transistor units.

12. The nonvolatile memory device of claim 11, wherein the memory blocks are arrayed in a first direction, and

the fifth, sixth and seventh pass transistor units are arrayed in the first direction.

13. The nonvolatile memory device of claim 8, wherein in each of the fifth, sixth, seventh and eighth pass transistor units, the pass transistors are arrayed in a second direction perpendicular to the first direction.

14. The nonvolatile memory device of claim 7, wherein the memory blocks are arrayed in a first direction,

each of the memory blocks has a dimension as measured along the first direction, and

each of the first, second and third pass transistor units has a dimension, along the first direction, greater than but less than twice that of each of the memory blocks.

15. A nonvolatile memory device comprising:

a memory cell array comprising blocks of cell strings, the blocks disposed side by side in a first direction in a horizontal plane, and each of the cell strings including a stack of respective memory transistors disposed one on another in a vertical direction perpendicular to the horizontal plane, and wherein each of the blocks has a plurality of the memory transistors located at each of a plurality of different levels arrayed in the vertical direction in the memory device,

groups of word lines connected to the blocks, respectively, wherein the word lines of each group are electrically connected to the memory transistors of a respective one of the blocks of cell strings;

a block gating unit including a plurality of circuits of pass transistors, and

wherein each of the circuits of pass transistors is connected to one of the blocks of cell strings,

respective ones of the pass transistors of the block gating unit are connected to the groups of word lines,

each of the circuits of pass transistors is disposed beside the blocks of cell strings along a second direction extending perpendicular to the first direction and the vertical direction, and

all of said pass transistors are disposed at the same level as one another in the memory device as arrayed in rows and columns in the first and second directions, respectively.

16. The nonvolatile memory device of claim 15, wherein the blocks of cell strings include first, second, third and fourth blocks of cell strings arrayed in the first direction in the foregoing order, the pass transistor circuits of the blocking gating unit include first, second, third and fourth pass transistor circuits disposed beside the first, second, third and fourth blocks of cell strings, respectively.

17. The nonvolatile memory device of claim 15, wherein the blocks of cell strings include first, second, third and fourth blocks of cell strings arrayed in the first direction in the foregoing order,

the pass transistor circuits of the blocking gating unit include first, second, third and fourth pass transistor circuits disposed beside the first, second, third and fourth blocks of cell strings, respectively.

18. The nonvolatile memory device of claim 15, wherein the blocks of cell strings include first, second, third and fourth blocks of cell strings arrayed in the first direction in the foregoing order,

the pass transistor circuits of the blocking gating unit include first, second, third and fourth pass transistor circuits,

the first and second pass transistors circuits are disposed side by side along the second direction and are each disposed beside both the first and second blocks of cell strings, and

the third and fourth pass transistors circuits are disposed side by side along the second direction and are each disposed beside both the third and fourth blocks of cell strings.

19. The nonvolatile memory device of claim 15, wherein the blocks of cell strings include first, second, third and fourth blocks of cell strings arrayed in the first direction in the foregoing order,

the pass transistor circuits of the blocking gating unit include first, second, third and fourth pass transistor circuits,

the first, second and third pass transistors circuits are arrayed in the first direction and are collectively disposed beside all four of the blocks of cell strings, and

the first, second and third pass transistors circuits are interposed in the first direction between the fourth pass transistor circuit and all four of the blocks of cell strings.