Multiport memory element circuitry

• US 9,576,617 B1
• Filed: 06/05/2014
• Issued: 02/21/2017
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Lee, Shih-Lin S., McElheny, Peter J., Singh, Preminder, Sinha, Shankar
• Primary Examiner(s): Alrobaie, Khamdan
• Application Number:
  US14/297,063
• Time in Patent Office: 992 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.

Claims

1. A method of accessing first and second memory elements, comprising:

asserting a word line signal on a word line that is coupled to the first and second memory elements, wherein the first and second memory elements each include a respective read access transistor;

providing a fixed body bias voltage to at least one transistor in the first memory element;

writing data into the first memory element by applying a first control voltage that weakens at least the read access transistor of the first memory element while the word line signal is asserted; and

preventing data from being written into the second memory element by applying a second control voltage to a body terminal of the read access transistor of the second memory element while the word line signal is asserted.

2. The method defined in claim 1, wherein the first memory element comprises a write access transistor, and wherein applying the first control voltage comprises applying a voltage that weakens the read access transistor of the first memory element without weakening the write access transistor in the first memory element.

3. The method defined in claim 1, wherein the first and second memory elements each include a respective write access transistor, and wherein applying the first control voltage comprises applying a voltage that weakens the read access transistor in the first memory element without weakening the write access transistor in the first memory element.

4. The method defined in claim 1, wherein the first and second memory elements each include a respective write access transistor, and wherein asserting the word line signal comprises asserting a control signal that turns on the write access transistor in the first memory element and that turns on the write access transistor in the second memory element.

5. The method defined in claim 4, further comprising:

asserting an additional word line signal on another word line that turns on the read access transistor in the first memory element and that turns on the read access transistor in the second memory element while the word line signal is asserted.

6. The method defined in claim 1, wherein the first control voltage has a first voltage level, and wherein the second control voltage has a second voltage level that is different than the first voltage level.

7. The method defined in claim 1, wherein applying the first control voltage comprises applying a first body biasing voltage to the read access transistor in the first memory element so that the read access transistor in the first memory element has a first drive strength, and wherein applying the second control voltage comprises applying a second body biasing voltage to the read access transistor in the second memory element so that that read access transistor in the second memory element has a second drive strength that is greater than the first drive strength.

8. Memory array circuitry, comprising:

a first data line;

a second data line that is different than the first data line;

first, second, and third wells;

a first memory cell that is coupled to the first data line and that is arranged in a given row, wherein the first memory cell includes first, second, and third transistors respectively formed in the first, second, and third wells, wherein the first transistor is a read access transistor, and wherein the second transistor is a write access transistor;

a second memory cell that is coupled to the second data line and that is arranged in the given row adjacent to the first memory cell;

an isolation well that is interposed between the first and second memory cells; and

control circuitry that provides an adjustable body bias voltage to the read access transistor and that provides a fixed body bias voltage to the write access transistor.

9. The memory array circuitry defined in claim 8, further comprising:

a first word line that is coupled to the first memory cell; and

a second word line that is different than the first word line and that is coupled to the second memory cell.

10. The memory array circuitry defined in claim 8, wherein the isolation well comprises an n-well.

11. The memory array circuitry defined in claim 8, wherein the first memory cell includes a group of n-channel transistors that receives an adjustable body bias voltage and a group of p-channel transistors that receives a fixed body bias voltage, wherein the group of n-channel transistors includes the first transistor in the first memory cell, and wherein the group of p-channel transistors includes the second transistor in the first memory cell.

12. The memory array circuitry defined in claim 11, wherein the first well comprises a p-well, wherein the second well comprises an n-well that is electrically isolated from the p-well, wherein the group of n-channel transistors is formed in the p-well, and wherein the group of p-channel transistors is formed in the n-well that is electrically isolated from the p-well.

13. An integrated circuit, comprising:

a first data line;

a second data line that is different than the first data line;

a first memory cell that is coupled to the first data line and that is arranged in a given row, wherein the first memory cell comprises a first read access transistor and a first write access transistor;

a second memory cell that is coupled to the second data line and that is arranged in the given row, wherein the second memory cell comprises a second read access transistor and a second write access transistor, and wherein the first and second memory cells share a common well;

an additional well that is separate from the common well, wherein the first read access transistor of the first memory cell is formed in the additional well, and wherein the first write access transistor of the first memory cell is formed in the common well; and

control circuitry that provides an adjustable body biasing voltage to the additional well and that also provides a fixed body biasing voltage to the common well.

14. The integrated circuit defined in claim 13, wherein the common well comprises a shared p-well.

15. The integrated circuit defined in claim 13, further comprising:

a word line that is coupled to the first and second memory cells.

16. The integrated circuit defined in claim 13, wherein the common well comprises a shared p-well, wherein the additional well comprises an additional p-well that is separate from the shared p-well.

17. The integrated circuit defined in claim 16, wherein the shared p-well is receives the fixed body biasing voltage, and wherein the additional p-well receives the adjustable body biasing voltage that weakens the read access transistor in the first memory cell during write operations.