Magnetic memory having ROM-like storage and method therefore

• US 9,576,636 B1
• Filed: 03/31/2016
• Issued: 02/21/2017
• Est. Priority Date: 04/03/2015
• Status: Active Grant

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Everspin Technologies Incorporated
• Inventors: Slaughter, Jon
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US15/087,469
• Time in Patent Office: 327 Days
• Field of Search: 365/158, 365/148, 365/170, 365/171, 365/207, 365/163
• US Class Current: 1/1
• CPC Class Codes: G11C 11/00 Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor G11C14/00 - G11C21/00 take precedence
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/18 using Hall-effect devices
• CPC Class Codes: G11C 11/5607 using magnetic storage elements
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods

Abstract

A magnetoresistive memory device that stores data in the reference portion of spin-torque memory cells provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, along with techniques for recovering data stored in the reference portions of memory cells.

Claims

1. A method of operation of a magnetoresistive memory, wherein the magnetoresistive memory includes plurality of non-volatile magnetoresistive memory cells, wherein each memory cell includes a reference portion and a free portion, wherein during normal operation, data is written into each memory cell by forcing a magnetic moment of the free portion into one of a parallel and an antiparallel orientation with respect to a magnetic moment of the reference portion, the method comprising:

lowering a switching barrier for the reference portion of each memory cell of the plurality of memory cells; and

after lowering the switching barrier;

for a first set of memory cells of the plurality of memory cells, applying a first current through each of the memory cells in the first set, wherein the first current is sufficient to force the reference portion of each memory cell to a first state.

2. The method of claim 1 further comprising:

for a second set of memory cells of the plurality of memory cells, applying a second current through each of the memory cells in the second set, wherein the second current is sufficient to force the reference portion of each memory cell to a second state.

3. The method of claim 1, further comprising:

before lowering the switching barrier, forcing the reference portion of each memory cell of the plurality of memory cells to a second state.

4. The method of claim 3, wherein forcing the reference portion of each memory cell of the plurality of memory cells to the second state includes applying an orienting magnetic field to the memory.

5. The method of claim 3, wherein lowering the switching barrier includes applying an external magnetic field to the memory, wherein the external magnetic field is insufficient to switch the reference layer of each memory cell from the second state to the first state without applying the first current through the memory cell.

6. The method of claim 5, wherein lowering the switching barrier includes exposing the memory to an elevated temperature while applying the external magnetic field, wherein a combination of the elevated temperature and the external magnetic field is insufficient to switch the reference layer of each memory cell from the second state to the first state without applying the first current through the memory cell.

7. The method of claim 1, wherein the reference portion of each memory cell of the plurality of memory cells includes an unpinned synthetic antiferromagnetic structure (SAF).

8. A method of operation of a magnetoresistive memory, wherein the magnetoresistive memory includes plurality of non-volatile magnetoresistive memory cells, wherein each memory cell includes a reference portion and a free portion, wherein during normal operation, data is written into each memory cell by forcing a magnetic moment of the free portion into one of a parallel and an antiparallel orientation with respect to a magnetic moment of the reference portion, the method comprising:

forcing the free portion of a selected memory cell of the plurality of memory cells to a known state corresponding to a known orientation of the magnetic moment of the free portion;

after forcing the free portion of the selected memory cell to the known state, sampling an initial resistance through a selected memory cell of the plurality of memory cells;

after sampling the initial resistance, applying a write current through the selected memory cell;

after applying the write current, sampling a resulting resistance through the selected memory cell; and

comparing the resulting resistance with the initial resistance to determine a state of the reference portion of the selected memory cell.

9. The method of claim 8, wherein forcing the free portion of the selected memory cell includes applying an external magnetic field to the memory, wherein the external magnetic field forces the free portion of each memory cell of the plurality of memory cells to the known state.

10. The method of claim 8, wherein applying the write current further comprises applying an up-current through the selected memory cell.

11. The method of claim 8, wherein the reference portion of each memory cell of the plurality of memory cells includes an unpinned synthetic antiferromagnetic structure (SAF).

12. A magnetoresistive memory, comprising:

a plurality of non-volatile magnetoresistive memory cells, wherein each memory cell includes a reference portion and a free portion, the plurality of memory cells including;

a first set of memory cells having a reference portion with a first magnetic state; and

a second set of memory cells having a reference portion with a second magnetic state, wherein the first magnetic state is different than the second magnetic state; and

control circuitry coupled to the plurality of memory cells, the control circuitry configured to read data stored in the reference portion of a first selected memory cell of the plurality of memory cells, wherein the control circuitry is configured to;

sample an initial resistance through the first selected memory cell;

after sampling the initial resistance, apply a first write current through the first selected memory cell;

after applying the first write current, sampling a resulting resistance through the first selected memory cell; and

comparing the resulting resistance with the initial resistance to determine whether the first selected memory cell is included in the first set of memory cells or the second set of memory cells.

13. The memory of claim 12, wherein each memory cell of the plurality of memory cells is a spin-torque magnetoresistive memory cell.

14. The memory of claim 13, wherein the reference portion of each memory cell includes an unpinned synthetic antiferromagnetic structure (SAF).

15. The memory of claim 12, wherein for each memory cell of the plurality of non-volatile magnetoresistive memory cells the reference portion and the free portion are such that when an external magnetic field of a selected magnitude is applied to the memory cell:

the free portion is held in a known magnetization state corresponding to the external magnetic field; and

the reference portion of the memory cell;

i) is forced to a programmed state when a current having a non-destructive magnitude is applied through the memory cell; and

ii) remains unchanged when the current having a non-destructive magnitude is not applied.

16. The memory of claim 12, wherein the control circuitry is further configured to write data into a second selected memory cell by applying a write current through the second selected memory cell to force the free portion of the second selected memory cell to have a magnetic moment that is either parallel or antiparallel to a magnetic moment of the reference portion of the second selected memory cell.

17. The memory of claim 16, wherein the control circuitry is further configured to read data stored in the free portion of the second selected memory cell using a self-referenced read that determines whether the magnetic moment of the free portion of the second selected memory cell is parallel or antiparallel to the magnetic moment of the reference portion of the second selected memory cell.

18. The memory of claim 12 further comprising data determination circuitry coupled to the plurality of memory cells and the control circuitry, wherein the data determination circuitry determines data stored in the memory by comparing a data state stored in the reference layer of a first memory cell with a data state stored in the reference layer of a second memory cell.

19. The memory of claim 18, wherein the data determination circuitry includes a majority detector, wherein the majority detector compares the data states of the first and second memory cells with a data state of at least a third memory cell.

20. The memory of claim 18 wherein the first memory cell and the second memory cell are a high-low pair of memory cells in which the first memory cell is referenced to the second memory cell.