Magnetic memory having ROM-like storage and method therefore
First Claim
1. A method of operation of a magnetoresistive memory, wherein the magnetoresistive memory includes plurality of non-volatile magnetoresistive memory cells, wherein each memory cell includes a reference portion and a free portion, wherein during normal operation, data is written into each memory cell by forcing a magnetic moment of the free portion into one of a parallel and an antiparallel orientation with respect to a magnetic moment of the reference portion, the method comprising:
- lowering a switching barrier for the reference portion of each memory cell of the plurality of memory cells; and
after lowering the switching barrier;
for a first set of memory cells of the plurality of memory cells, applying a first current through each of the memory cells in the first set, wherein the first current is sufficient to force the reference portion of each memory cell to a first state.
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Accused Products
Abstract
A magnetoresistive memory device that stores data in the reference portion of spin-torque memory cells provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, along with techniques for recovering data stored in the reference portions of memory cells.
13 Citations
20 Claims
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1. A method of operation of a magnetoresistive memory, wherein the magnetoresistive memory includes plurality of non-volatile magnetoresistive memory cells, wherein each memory cell includes a reference portion and a free portion, wherein during normal operation, data is written into each memory cell by forcing a magnetic moment of the free portion into one of a parallel and an antiparallel orientation with respect to a magnetic moment of the reference portion, the method comprising:
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lowering a switching barrier for the reference portion of each memory cell of the plurality of memory cells; and after lowering the switching barrier; for a first set of memory cells of the plurality of memory cells, applying a first current through each of the memory cells in the first set, wherein the first current is sufficient to force the reference portion of each memory cell to a first state. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of operation of a magnetoresistive memory, wherein the magnetoresistive memory includes plurality of non-volatile magnetoresistive memory cells, wherein each memory cell includes a reference portion and a free portion, wherein during normal operation, data is written into each memory cell by forcing a magnetic moment of the free portion into one of a parallel and an antiparallel orientation with respect to a magnetic moment of the reference portion, the method comprising:
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forcing the free portion of a selected memory cell of the plurality of memory cells to a known state corresponding to a known orientation of the magnetic moment of the free portion; after forcing the free portion of the selected memory cell to the known state, sampling an initial resistance through a selected memory cell of the plurality of memory cells; after sampling the initial resistance, applying a write current through the selected memory cell; after applying the write current, sampling a resulting resistance through the selected memory cell; and comparing the resulting resistance with the initial resistance to determine a state of the reference portion of the selected memory cell. - View Dependent Claims (9, 10, 11)
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12. A magnetoresistive memory, comprising:
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a plurality of non-volatile magnetoresistive memory cells, wherein each memory cell includes a reference portion and a free portion, the plurality of memory cells including; a first set of memory cells having a reference portion with a first magnetic state; and a second set of memory cells having a reference portion with a second magnetic state, wherein the first magnetic state is different than the second magnetic state; and control circuitry coupled to the plurality of memory cells, the control circuitry configured to read data stored in the reference portion of a first selected memory cell of the plurality of memory cells, wherein the control circuitry is configured to; sample an initial resistance through the first selected memory cell; after sampling the initial resistance, apply a first write current through the first selected memory cell; after applying the first write current, sampling a resulting resistance through the first selected memory cell; and comparing the resulting resistance with the initial resistance to determine whether the first selected memory cell is included in the first set of memory cells or the second set of memory cells. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification