Fine granularity refresh

• US 9,576,637 B1
• Filed: 05/25/2016
• Issued: 02/21/2017
• Est. Priority Date: 05/25/2016
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Balakrishnan, Kedarnath
• Primary Examiner(s): Nguyen, Hien
• Application Number:
  US15/164,721
• Time in Patent Office: 272 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 2207/2272 Latency related aspects

Abstract

A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. In response to an activation of the refresh logic, the data processor generates refresh cycles to a bank of the memory channel. The data processor selects one of a first state corresponding to a first auto-refresh command that causes the data processor to auto-refresh the bank, and a second state corresponding to a second auto-refresh command that causes the data processor to auto-refresh a selected subset of the bank. The data processor initiates a switch between the first state and the second state in response to the refresh logic detecting a first condition related to the bank, and between the second state and the first state in response to the refresh logic circuit detecting a second condition.

Claims

1. A data processing system, comprising:

a memory channel comprising at least one rank; and

a data processor coupled to said memory channel and adapted to access said at least one rank said data processor having refresh logic, wherein in response to an activation of said refresh logic, said data processor;

generates refresh cycles to a bank of said memory channel, wherein said data processor selects one of a first state and a second state, wherein said first state corresponds to a first auto-refresh command that causes said data processor to auto-refresh said bank, and said second state corresponds to a second auto-refresh command that causes said data processor to auto-refresh a selected subset of said bank;

initiates a switch between said first state and said second state in response to said refresh logic detecting a first condition related to said bank; and

initiates a switch between said second state and said first state in response to a detection of a second condition.

2. The data processing system of claim 1, wherein said refresh logic detects said first condition in response to a number of pending refreshes to said bank being above a predetermined threshold.

3. The data processing system of claim 1, wherein:

said refresh logic detects said second condition in response to a number of refreshes sent to said bank corresponds to a total number of subsets of said bank; and

said data processor stores no access request to said bank.

4. The data processing system of claim 1, wherein:

said data processor refreshes a first subset and a second subset of said bank within a refresh cycle time when said second auto-refresh command is a refresh two (REF2) command; and

each of said first subset and said second subset of said bank is a separate half subset of said bank.

5. The data processing system of claim 4, wherein:

said data processor refreshes said first subset, said second subset, a third subset, and a fourth subset of said bank within said refresh cycle time when said second auto-refresh command is a refresh four (REF4) command; and

each of said first subset, said second subset, said third subset, and said fourth subset of said bank is a separate quarter subset of said bank.

6. The data processing system of claim 1, wherein said data processor detects said first condition in response to one or more of:

a number of pending refreshes to said bank, a number of pending requests to said bank, a priority of said pending requests to said bank, and a type of said pending requests to said bank.

7. The data processing system of claim 6, wherein said data processor tracks said number of pending refreshes to said bank to determine an initiation of a switch between said first state and said second state.

8. The data processing system of claim 1, wherein said second auto-refresh command refreshes said selected subset of said bank of one rank.

9. The data processing system of claim 1, wherein said second auto-refresh command refreshes said selected subset of a plurality of banks of one rank.

10. The data processing system of claim 1, wherein said second auto-refresh command refreshes said selected subset of a corresponding bank of each of a plurality of ranks.

11. The data processing system of claim 1, wherein said memory channel (130) comprises a plurality of ranks of double rate (DDR) version four (DDR4) memory.

12. A data processor comprising:

a memory accessing agent; and

a memory controller coupled to said memory accessing agent and adapted to couple to a memory system, wherein said memory controller;

comprises a refresh logic circuit for generating refresh cycles to a memory of the memory system, having an on-the-fly mode wherein said on-the-fly mode comprises a first state and a second state, said first state corresponding to a first auto-refresh command that causes said memory to auto-refresh a bank, said second state corresponding to a second auto-refresh command that causes said memory to auto-refresh a selected subset of said bank;

switches between said first state and said second state in response to said refresh logic circuit detecting a first condition related to said bank of said memory system; and

switches between said second state and said first state in response to refresh logic circuit detecting a second condition.

13. The data processor of claim 12, wherein said refresh logic circuit detects said first condition in response to a number of pending refreshes to said bank being above a predetermined threshold.

14. The data processor of claim 12, wherein said refresh logic circuit detects said second condition in response to a number of pending refreshes to said bank.

15. The data processor of claim 12, wherein:

said memory controller is adapted to refresh a first subset and a second subset of said bank within a refresh cycle time, when said second auto-refresh command is a refresh two (REF2) command; and

each of said first subset and said second subset of said bank is a separate half subset of said bank.

16. The data processor of claim 12, wherein:

said memory controller is adapted to refresh a first subset, a second subset, a third subset, and a fourth subset of said bank within a refresh cycle time when said second auto-refresh command is a refresh four (REF4) command; and

each of said first subset, said second subset, said third subset, and said fourth subset of said bank is a separate quarter subset of said bank.

17. The data processor of claim 12, wherein said memory controller detects said first condition in response to one or more of:

a number of pending refreshes to said bank, a number of pending requests to said bank, a priority of said pending requests to said bank, and a type of said pending requests to said bank.

18. The data processor of claim 17, wherein said memory controller tracks said number of pending refreshes to said bank to determine an initiation of a switch between said first state and said second state.

19. The data processor of claim 12, wherein said second auto-refresh command refreshes said selected subset of said bank of one rank.

20. The data processor of claim 12, wherein said second auto-refresh command refreshes said selected subset of a plurality of banks of one rank.

21. The data processor of claim 12, wherein said second auto-refresh command refreshes said selected subset of a corresponding bank of each of a plurality of ranks.

22. A method for managing refresh of a memory in a memory system via a memory controller, the method comprising:

generating a first auto-refresh command when the memory controller is in a first state, wherein said first auto-refresh command causes the memory to auto-refresh a bank,

generating a second auto-refresh command when the memory controller is in a second state, wherein said second auto-refresh command causes the memory to auto-refresh a selected subset of said bank,

switching between said first state and said second state in response to the memory controller detecting a first condition related to said bank; and

switching between said second state and said first state in response to the memory controller detecting a second condition.

23. The method of claim 22, wherein said detecting said first condition comprises:

detecting when a number of pending refreshes to said bank are above a predetermined threshold.

24. The method of claim 22, wherein said detecting said second condition comprises:

detecting that a number of refreshes sent corresponds to a total number of subsets of said bank; and

detecting that the memory controller stores no access request to said bank.

25. The method of claim 22, wherein generating said second auto-refresh command comprises:

refreshing a first subset and a second subset of said bank within a refresh period when said second auto-refresh command is a refresh two (REF2) command, wherein each of said first subset and said second subset of said bank is a separate half subset of said bank.

26. The method of claim 22, wherein generating said second auto-refresh command comprises:

refreshing a first subset, a second subset, a third subset, and a fourth subset of said bank within a refresh period when said second auto-refresh command is a refresh two (REF2) command, wherein said first subset, said second subset, said third subset, and said fourth subset of said bank is a separate quarter subset of said bank.

27. The method of claim 22, further comprising:

detecting said first condition in response to one or more of;

a number of pending refreshes to said bank, a number of pending requests to said bank, a priority of said pending requests to said bank, and a type of said pending requests to said bank.

28. The method of claim 22, further comprising refreshing said selected subset of said bank of one rank in response to said generating said second auto-refresh command.

29. The method of claim 22, further comprising refreshing said selected subset of a plurality of banks of one rank in response to said generating said second auto-refresh command.

30. The method of claim 22, further comprising refreshing said selected subset of a corresponding bank of each of a plurality of ranks in response to said generating said second auto-refresh command.

31. The method of claim 22, further comprising:

performing said generating said first auto-refresh command, said generating said second auto-refresh command, said switching between said first state and said second state, and said switching between said second state and said first state independently for each of a plurality of banks of the memory.