Non-volatile memory device, operating method thereof, memory system including the non-volatile memory device, and operating method of the memory system

• US 9,576,666 B2
• Filed: 02/29/2016
• Issued: 02/21/2017
• Est. Priority Date: 06/22/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shim, Young-Seop, Kim, Jae-Hong
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US15/055,747
• Publication Number:
  US 20160372199A1
• Time in Patent Office: 358 Days
• Field of Search: 365/185.09, 365/185.17
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

An operating method of a non-volatile memory device having a string including a plurality of memory cells and a plurality of auxiliary cells, the plurality of memory cells and the plurality of auxiliary cells being connected in series, includes detecting a threshold voltage of at least one of the plurality of auxiliary cells and generating an output signal corresponding to a deterioration level of the plurality of memory cells, based on the threshold voltage.

Claims

1. An operating method of a non-volatile memory device comprising a string having a plurality of memory cells and a plurality of auxiliary cells, the plurality of memory cells and the plurality of auxiliary cells being connected in series, the operating method comprising:

detecting a threshold voltage of an auxiliary cell among the auxiliary cells; and

generating an output signal corresponding to a deterioration level of the plurality of memory cells, based on the threshold voltage.

2. The operating method of claim 1, wherein:

the plurality of auxiliary cells comprises a string selection transistor arranged at an end of the string and connected to a bit line, and

the output signal indicates a deterioration of the plurality of memory cells when the threshold voltage of the string selection transistor is less than a predetermined reference value.

3. The operating method of claim 1, wherein:

the plurality of auxiliary cells comprises a ground selection transistor, arranged at an end of the string and connected to a source line, and a dummy cell between the ground selection transistor and the plurality of memory cells, and

the output signal indicates a deterioration of the plurality of memory cells when the threshold voltage of the dummy cell is greater than a predetermined reference value.

4. The operating method of claim 1, wherein:

the non-volatile memory device further comprises a memory block comprising a plurality of strings, and

the generating of the output signal comprises;

counting the number of strings comprising an auxiliary cell having a threshold voltage greater than a predetermined reference value, from among the plurality of strings, or counting the number of the strings having the threshold voltage less than the reference value, and

generating the counted number of strings as the output signal.

5. The operating method of claim 1, further comprising:

receiving a command or a control signal from outside of the non-volatile memory device; and

outputting the output signal to the outside of the non-volatile memory device, wherein

the detecting of the threshold voltage and the generating of the output signal are performed in response to the command or the control signal.

6. The operating method of claim 1, further comprising:

counting the number of times erasing is performed on the plurality of memory cells; and

storing data corresponding to the output signal in a count storage unit within the non-volatile memory device, wherein

the detecting of the threshold voltage and the generating of the output signal are performed when the number of times erasing is performed on the plurality of memory cells is one of a plurality of predetermined reference counts.

7. The operating method of claim 6, further comprising:

receiving a command or a control signal from outside of the non-volatile memory device; and

outputting a signal corresponding to the data stored in the count storage unit to the outside of the non-volatile memory device, in response to the command or the control signal.

8. The operating method of claim 6, wherein the plurality of predetermined reference counts are multiples of n, wherein n is an integer greater than 1.

9. The operating method of claim 1, wherein the detecting of the threshold voltage comprises:

precharging a bit line connected to the string;

applying a pass voltage to each of word lines connected to the plurality of memory cells;

applying a read voltage which is less than the pass voltage to a gate line connected to the auxiliary cell; and

sensing a voltage of the bit line.

10. The operating method of claim 9, further comprising:

receiving a command or a control signal from outside of the non-volatile memory device; and

changing the read voltage which is to be applied to the gate line, in response to the command or the control signal.

11. An operating method of a memory system comprising a non-volatile memory device and a memory controller configured to control the non-volatile memory device, the non-volatile memory device comprising a string having a plurality of memory cells and a plurality of auxiliary cells, the plurality of memory cells and the plurality of auxiliary cells being connected in series, the operating method comprising:

generating, via the non-volatile memory device, an output signal corresponding to a deterioration level of the plurality of memory cells, based on a threshold voltage of an auxiliary cell among the auxiliary cells;

transmitting, via the non-volatile memory device, the output signal to the memory controller;

determining, via the memory controller, the deterioration level of the plurality of memory cells based on the output signal; and

controlling, via the memory controller, the non-volatile memory device based on the determined deterioration level.

12. The operating method of claim 11, wherein:

the plurality of auxiliary cells comprises a string selection transistor at an end of the string and connected to a bit line, and

the output signal indicates a deterioration of the plurality of memory cells when the threshold voltage of the string selection transistor is less than a predetermined reference value.

13. The operating method of claim 11, wherein:

the plurality of auxiliary cells comprises a ground selection transistor, arranged at an end of the string and connected to a source line, and a dummy cell between the ground selection transistor and the plurality of memory cells, and

the output signal indicates a deterioration of the plurality of memory cells when the threshold voltage of the dummy cell is higher than a predetermined reference value.

14. The operating method of claim 11, further comprising:

transmitting, via the memory controller, a command or a control signal to the non-volatile memory device, wherein

the generating of the output signal and the transmitting of the output signal are performed in response to the command or the control signal.

15. The operating method of claim 14, wherein:

the non-volatile memory device comprises a memory block comprising a plurality of strings, and

the operating method further comprises;

counting, via the memory controller, the number of times erasing is performed on the memory block, and

the transmitting of the command or the control signal and the determining of the deterioration level are performed when the number of times erasing is performed on the memory block is one of a plurality of predetermined reference counts.

16. The operating method of claim 15, wherein the generating of the output signal via the non-volatile memory device comprises:

counting the number of strings, each comprising an auxiliary cell, having a threshold voltage greater than a predetermined reference value, from among the plurality of strings, or counting the number of the strings having the threshold voltage which is less than the reference value, and

generating the counted number of strings as the output signal.

17. The operating method of claim 16, wherein:

the memory system comprises a look-up table configured to store numbers of strings which respectively correspond to the plurality of predetermined reference counts and a deterioration level storage unit configured to store deterioration information of the memory block, and

the determining of the deterioration level via the memory controller comprises;

reading, from the look-up table, a number of first strings corresponding to the number of times erasing is performed on the memory block, and

comparing the number of first strings with a number of second strings corresponding to the output signal, and when the number of second strings is greater than the number of first strings, updating data stored in the deterioration level storage unit.

18. The operating method of claim 17, wherein the controlling of the non-volatile memory device via the memory controller comprises selecting a memory block, among a plurality of memory blocks, to be erased via the non-volatile memory device, based on the data stored in the deterioration level storage unit.

19. The operating method of claim 17, wherein the controlling of the non-volatile memory device via the memory controller comprises selecting a memory block, among a plurality of memory blocks, to which data is to be written via the non-volatile memory device, based on the data stored in the deterioration level storage unit.

20. The operating method of claim 15, wherein the plurality of predetermined reference counts are multiples of n, wherein n is an integer greater than 1.