Systems and methods for hard error reduction in a solid state memory device

• US 9,576,683 B2
• Filed: 02/11/2014
• Issued: 02/21/2017
• Est. Priority Date: 02/06/2014
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Wu, Yunxiang, Cai, Yu, Haratsch, Erich F.
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US14/178,201
• Publication Number:
  US 20150220388A1
• Time in Patent Office: 1,106 Days
• Field of Search: 714/773, 714/764, 714/49, 714/719, 711/103, 365/185.03, 365/185.18, 365/185.2, 365/185.12, 365/185.24, 365/185.02, 365/185.11, 365/185.22, 365/185.29, 365/189.07
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/14 : Dummy cell management; Sense reference voltage generators

Abstract

Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory.

Claims

1. A method for writing data to a solid state memory device, the method comprising:

programming a multi-bit cell of a memory device with a first value selected based upon a first bit value;

reading the multi-bit cell of the memory device using a first selected reference value as a first reference voltage to yield a first read data;

compare the first bit value with the first read data to determine a first bit error rate;

store the first bit error rate;

reading the multi-bit cell of the memory device using a second selected reference value as a second reference voltage to yield a second-read data;

compare the first bit value with the second read data to determine a second bit error rate;

compare the first bit error rate to the second bit error rate and determine which has a lowest bit error rate; and

setting a modified reference value based on a reference value that yields the lowest bit error rate, the modified reference value to be utilized for future writes to the solid state memory device.

2. The method of claim 1, wherein programming a multi-bit cell of the memory device with the first value further comprises:

erasing the two or more multi-bit cells of the selected region of the memory device.

3. The method of claim 1, wherein a first distribution corresponding to a first programming level of the two or more cells of the selected region of the memory device and a second distribution corresponding to a second programming level of the two or more multi-bit cells of the selected region of the memory device overlap.

4. The method of claim 3, wherein a lower of the first bit error rate and the second bit error rate is selected to correspond to a test value that is closer to the intersection of the first distribution and the second distribution.

5. The method of claim 1, wherein the multi-bit cell of the memory device is a two-bit cell.

6. The method of claim 1, wherein the multi-bit cell of the memory device is a three-bit cell.

7. The method of claim 1 further comprising

receiving a write request and associated write data;

programming a lower page of the multi-bit cell of the memory device with a least significant bit of the write data;

reading the lower page using a predetermined reference value as a reference voltage to yield a lower page read data; and

selecting a target voltage for writes to the multi-bit cell of the memory device based upon a combination of a most significant bit of the write data and the lower page read data; and

modifying the predetermined reference value based upon the method of claim 1.

8. A data storage system, the system comprising:

a memory device;

a memory device access circuit configured to;

program a multi-bit cell of a memory device with a first value selected based upon a first bit value;

read the multi-bit cell of the memory device using a first reference value as a reference voltage to yield a read data;

select a target voltage for writes to the multi-bit cell of the memory device based upon a combination of a second bit value and the read data; and

a reference control circuit configured to modify the target voltage based on a bit error rate of a test region of the memory device.

9. The system of claim 8, wherein at least the memory device access circuit and the reference control circuit are incorporated in an integrated circuit.

10. The system of claim 8, wherein the system is implemented on an integrated circuit.

11. The system of claim 8, wherein the memory device is a flash memory device.

12. The system of claim 8, wherein modifying the target voltage includes:

programming two or more multi-bit cells of a selected region of the memory device with a known pattern;

reading back the two or more multi-bit cells of the selected region of the memory device using a first test value as a reference voltage to yield a first read back data set;

comparing the first read back data set with the known pattern;

generating a first bit error rate corresponding to the first test value based upon the comparison of the first read back data set with the known pattern;

reading back the two or more multi-bit cells of the selected region of the memory device using a second test value as a reference voltage to yield a second read back data set;

comparing the second read back data set with the known pattern; and

generating a second bit error rate corresponding to the second test value based upon the comparison of the second read back data set with the known pattern.

13. The system of claim 8, wherein the memory device access circuit is further configured to:

erase the multi-bit cell of the memory device prior to programming the multi-bit cell of the memory device with the first value.

14. The system of claim 12, wherein the reference control circuit further configured to:

select one of the first test value or the second test value as a modified target value based at least in part on a comparison of the first bit error rate and the second bit error rate.

15. The system of claim 12, wherein a first distribution corresponding to a first programming level of the two or more multi-bit cells of the selected region of the memory device and a second distribution corresponding to a second programming level of the two or more multi-bit cells of the selected region of the memory device overlap.

16. The system of claim 12, wherein a lower of the first bit error rate and the second bit error rate corresponds to a test value that is closer to the intersection of the first distribution and the second distribution.

17. The system of claim 8, wherein the multi-bit cell of the memory device is a two-bit cell.

18. The system of claim 8, wherein the multi-bit cell of the memory device is a three-bit cell.

19. A flash memory storage system, the system comprising:

a memory device including a plurality of multi-bit flash memory cells;

a memory device access circuit configured to;

program a multi-bit flash memory cell of the memory device with a first value selected based upon a first bit value;

read the multi-bit flash memory cell of the memory device using a target reference value to yield a read data;

program the multi-bit flash memory cell of the memory device with a second value selected based upon a combination of a second bit value and the read data; and

a reference control circuit configured to modify the target reference value and configured to;

program two or more multi-bit flash memory cells of a selected region of the memory device with a known pattern;

read back the two or more multi-bit flash memory cells of the selected region of the memory device using a first test value as a reference voltage to yield a first read back data set;

compare the first read back data set with the known pattern;

generate a first bit error rate corresponding to the first test value based upon the comparison of the first read back data set with the known pattern;

read back the two or more multi-bit flash memory cells of the selected region of the memory device using a second test value as a reference voltage to yield a second read back data set;

compare the second read back data set with the known pattern;

generate a second bit error rate corresponding to the second test value based upon the comparison of the second read back data set with the known pattern; and

select the one of the first test value or the second test value as the target reference value based at least in part on a comparison of the first bit error rate and the second bit error rate.

20. The flash memory storage system of claim 19, wherein the reference control circuit is further configured to select the one of the first test value or the second test value as the target reference value by selecting one of the first test value or the second test value that yields a lowest bit error rate.