Memory device having electrically floating body transistor
First Claim
1. A semiconductor memory cell comprising:
- a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
a first region in electrical contact with said floating body region; and
a back-bias region configured to maintain a charge in said floating body region;
wherein said first region, said floating body region, and said back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of said bipolar transistor approaches unity, andwherein said back bias region has a lower band gap than said floating body region.
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Abstract
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.
229 Citations
19 Claims
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1. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with said floating body region; and a back-bias region configured to maintain a charge in said floating body region; wherein said first region, said floating body region, and said back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of said bipolar transistor approaches unity, and wherein said back bias region has a lower band gap than said floating body region. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a back bias region; wherein said floating body region acts as a base region of a first bipolar transistor that maintains the state of said memory cell; wherein said back-bias region acts as a collector region of said first bipolar transistor and has a lower band gap than said floating body region; and wherein said floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of said memory cell. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and a back-bias region located below said floating body region; wherein said back-bias region acts as a collector region of a bipolar transistor that maintains the state of said memory cell and has a lower band gap than said floating body region. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification