FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure

• US 9,576,980 B1
• Filed: 08/20/2015
• Issued: 02/21/2017
• Est. Priority Date: 08/20/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Basker, Veeraraghavan S., Cheng, Kangguo, Standaert, Theodorus E., Wang, Junli
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US14/830,868
• Publication Number:
  US 20170053941A1
• Time in Patent Office: 551 Days
• Field of Search: 438/157, 257/310, 257/392
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

FinFET devices are formed on the same semiconductor structure wherein at least one finFET device has a gate dielectric structure that is different in thickness relative to a gate dielectric structure of at least one other finFET device. The finFET devices are formed as part of the same fabrication process.

Claims

1. A method, comprising steps of:

forming a first finFET device on a substrate structure wherein the first finFET device comprises a first gate dielectric structure having a first thickness; and

forming a second finFET device on the substrate structure wherein the second finFET device comprises a second gate dielectric structure having a second thickness;

wherein the first thickness and the second thickness are different, and the first finFET device forming step and the second finFET device forming step are part of the same fabrication process; and

wherein forming the first and second finFET devices further comprises;

forming respective fin structures on the substrate structure;

forming respective pairs of spacers proximate to the respective fin structures;

depositing dummy oxide layers on the respective fin structures;

depositing dummy gate polysilicon layers over the dummy oxide layers; and

depositing inner-layer dielectric layers adjacent to the respective pairs of spacers.

2. The method of claim 1, wherein the substrate structure is an insulated substrate structure comprising an insulator layer deposited on a silicon substrate.

3. The method of claim 2, wherein the insulator layer is a buried oxide material.

4. The method of claim 1, wherein the first thickness is greater than the second thickness.

5. The method of claim 1, wherein the first gate dielectric structure is a thick gate dielectric structure, and the second gate dielectric structure is a thin gate dielectric structure.

6. The method of claim 5, wherein the thick gate dielectric structure comprises a first dielectric layer and a second dielectric layer.

7. The method of claim 6, wherein the thin gate dielectric structure comprises the second dielectric layer.

8. The method of claim 6, wherein the first dielectric layer and the second dielectric layer are high-k dielectric layers.

9. The method of claim 1, wherein forming the first and second finFET devices further comprises:

removing the dummy oxide layers and the dummy gate polysilicon layers from the respective fin structures;

depositing a first dielectric layer on the respective fin structures; and

depositing a titanium nitride layer over the first dielectric layer.

10. The method of claim 9, wherein forming the first and second finFET devices further comprises:

forming a resist mask over the first finFET device to protect the titanium nitride layer and the first dielectric layer on the first finFET device; and

removing the titanium nitride layer and the first dielectric layer from the second finFET device.

11. The method of claim 10, wherein forming the first and second finFET devices further comprises removing the resist mask and the titanium nitride layer from the first finFET device.

12. The method of claim 11, wherein forming the first and second finFET devices further comprises:

depositing a second dielectric layer over the first and second finFET devices; and

forming respective metal gates for the first and second finFET devices.

13. A method comprising:

forming a first finFET device on a substrate structure wherein the first finFET device comprises a first gate dielectric structure having a first thickness; and

forming a second finFET device on the substrate structure wherein the second finFET device comprises a second gate dielectric structure having a second thickness;

wherein the first thickness and the second thickness are different, and the first finFET device forming step and the second finFET device forming step are part of the same fabrication process; and

wherein forming the first and second finFET devices further comprises;

forming respective fin structures on the substrate structure;

forming respective pairs of spacers proximate to the respective fin structures;

depositing first dielectric layers on the respective fin structures;

depositing dummy gate polysilicon layers over the respective first dielectric layers;

depositing inner-layer dielectric layers adjacent to the respective pairs of spacers;

removing the dummy gate polysilicon layers; and

depositing a titanium nitride layer over the respective first dielectric layers.

14. The method of claim 13, wherein forming the first and second finFET devices further comprises:

forming a resist mask over the first finFET device to protect the titanium nitride layer and the first dielectric layer on the first finFET device;

removing the titanium nitride layer and the first dielectric layer from the second finFET device;

removing the resist mask and the titanium nitride layer from the first finFET device;

depositing a second dielectric layer over the first and second finFET devices; and

forming respective metal gates for the first and second finFET devices.

15. The method of claim 13, wherein the substrate structure is an insulated substrate structure comprising an insulator layer deposited on a silicon substrate.

16. The method of claim 15, wherein the insulator layer is a buried oxide material.

17. The method of claim 13, wherein the first gate dielectric structure is a thick gate dielectric structure, and the second gate dielectric structure is a thin gate dielectric structure.

18. The method of claim 17, wherein the thick gate dielectric structure comprises a first dielectric layer and a second dielectric layer.

19. The method of claim 18, wherein the thin gate dielectric structure comprises the second dielectric layer.

20. The method of claim 18, wherein the first dielectric layer and the second dielectric layer are high-k dielectric layers.