Semiconductor device having a gate insulting film with thick portions aligned with a tapered gate electrode

• US 9,576,981 B2
• Filed: 01/06/2014
• Issued: 02/21/2017
• Est. Priority Date: 07/22/1999
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Suzawa, Hideomi, Ono, Koji, Arai, Yasuyuki
• Primary Examiner(s): Miyoshi, Jesse Y
• Application Number:
  US14/147,799
• Publication Number:
  US 20140117364A1
• Time in Patent Office: 1,142 Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1277 using a crystallisation promoting species, e.g. local introduction of Ni catalyst
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78645 with multiple gate

Abstract

By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

Claims

1. A semiconductor device comprising:

a transistor comprising;

a first semiconductor layer including a pair of LDD regions, a channel region between the pair of LDD regions, and source and drain regions;

an insulating layer over the first semiconductor layer; and

a gate electrode over the insulating layer, the gate electrode including a first tapered side surfaces; and

a capacitor comprising;

a second semiconductor layer including an impurity region, the second semiconductor layer being contiguous with the first semiconductor layer; and

a capacitor wiring over the second semiconductor layer, the capacitor wiring including a second tapered side surfaces,

wherein the insulating layer includes a first region overlapping the channel region and a second region overlapping one of the source and drain regions, and

wherein a thickness of the first region is thicker than the second region.

2. The semiconductor device according to claim 1, further comprising:

an interlayer insulating layer over the gate electrode; and

a pixel electrode over the interlayer insulating layer, the pixel electrode electrically connected to the first semiconductor layer.

3. The semiconductor device according to claim 2, further comprising:

a wiring over the interlayer insulating layer, the wiring in contact with one of the source and drain regions,

wherein the pixel electrode is electrically connected to the first semiconductor layer thorough the wiring.

4. The semiconductor device according to claim 3, wherein the wiring overlaps the pixel electrode.

5. The semiconductor device according to claim 3, wherein the pixel electrode overlaps the wiring.

6. The semiconductor device according to claim 1, wherein an angle of each of the first tapered side surfaces is in a range between 5°

and 45°

with respect to a surface of the insulating layer.

7. A semiconductor device comprising:

a transistor comprising;

a first semiconductor layer including a pair of LDD regions, a channel region between the pair of LDD regions, and source and drain regions;

an insulating layer over the first semiconductor layer; and

a gate electrode over the insulating layer, the gate electrode including a first tapered side surfaces; and

a capacitor comprising;

a second semiconductor layer including an impurity region, the second semiconductor layer being contiguous with the first semiconductor layer; and

a capacitor wiring over the second semiconductor layer, the capacitor wiring including a second tapered side surfaces,

wherein the insulating layer includes a first region overlapping the channel region and a second region overlapping one of the source and drain regions,

wherein a thickness of the first region is thicker than the second region,

wherein the first tapered side surfaces of the gate electrode and the pair of LDD regions overlap each other, and

wherein a side edge of the gate electrode aligns with both a side edge of the first region and a side edge of the channel region.

8. The semiconductor device according to claim 7, further comprising:

an interlayer insulating layer over the gate electrode; and

a pixel electrode over the interlayer insulating layer, the pixel electrode electrically connected to the first semiconductor layer.

9. The semiconductor device according to claim 8, further comprising:

a wiring over the interlayer insulating layer, the wiring in contact with one of the source and drain regions,

wherein the pixel electrode is electrically connected to the first semiconductor layer thorough the wiring.

10. The semiconductor device according to claim 9, wherein the wiring overlaps the pixel electrode.

11. The semiconductor device according to claim 9, wherein the pixel electrode overlaps the wiring.

12. The semiconductor device according to claim 7, wherein an angle of each of the first tapered side surfaces is in a range between 5°

and 45°

with respect to a surface of the insulating layer.

13. A semiconductor device comprising:

a transistor comprising;

a first semiconductor layer on an insulating surface, the first semiconductor layer including a pair of LDD regions, a channel region between the pair of LDD regions, and source and drain regions;

an insulating layer over the first semiconductor layer; and

a gate electrode over the insulating layer, the gate electrode including a first tapered side surfaces; and

a capacitor comprising;

a second semiconductor layer including an impurity region, the second semiconductor layer being contiguous with the first semiconductor layer; and

a capacitor wiring over the second semiconductor layer, the capacitor wiring including a second tapered side surfaces,

wherein the insulating layer includes a first region overlapping the channel region and a second region overlapping one of the source and drain regions,

wherein a thickness of the first region is thicker than the second region,

wherein angles of the first tapered side surfaces of the gate electrode with respect to the insulating surface is different from angles of side surfaces of the first region of the insulating layer, and

wherein a side edge of the gate electrode aligns with both a side edge of the first region and a side edge of the channel region.

14. The semiconductor device according to claim 13, further comprising:

an interlayer insulating layer over the gate electrode; and

a pixel electrode over the interlayer insulating layer, the pixel electrode electrically connected to the first semiconductor layer.

15. The semiconductor device according to claim 14, further comprising:

a wiring over the interlayer insulating layer, the wiring in contact with one of the source and drain regions,

wherein the pixel electrode is electrically connected to the first semiconductor layer thorough the wiring.

16. The semiconductor device according to claim 15, wherein the wiring overlaps the pixel electrode.

17. The semiconductor device according to claim 15, wherein the pixel electrode overlaps the wiring.

18. The semiconductor device according to claim 13, wherein an angle of each of the first tapered side surfaces is in a range between 5°

and 45°

with respect to a surface of the insulating layer.

19. The semiconductor device according to claim 13, wherein the angles of the side surfaces of the first region is perpendicular to the insulating surface.