Cross-point memory and methods for fabrication of same

• US 9,577,010 B2
• Filed: 02/25/2014
• Issued: 02/21/2017
• Est. Priority Date: 02/25/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sciarrillo, Samuele
• Primary Examiner(s): LUKE, DANIEL M
• Application Number:
  US14/189,265
• Publication Number:
  US 20150243885A1
• Time in Patent Office: 1,092 Days
• US Class Current: 1/1
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/32 of the bipolar type
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/882 Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8822 Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.

Claims

1. A memory device, comprising:

a semiconductor substrate;

a memory cell stack formed between and electrically connected to first and second conductive lines, the memory cell stack comprising;

a first memory element over the semiconductor substrate,

a second memory element formed over the first memory element,

a first pair of sidewalls associated with the first memory element opposing each other;

a first protective dielectric insulating material formed on a lower portion of the first pair of sidewalls;

a second pair of sidewalls associated with the first memory element opposing each other;

a second protective dielectric insulating material formed on a lower portion of the second pair of sidewalls, the second protective dielectric insulating material intersecting the first protective dielectric insulating material;

wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element, the first memory element being closer to the semiconductor substrate than the second memory element; and

an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.

2. The memory device of claim 1, wherein the first memory element comprises the selector element and the second memory element comprises the storage element.

3. The memory device of claim 2, wherein the first protective dielectric insulating material is formed on sidewalls of the selector element while not being formed on sidewalls of the storage element.

4. The memory device of claim 2, wherein the memory device is a phase change memory device, and wherein the first memory element comprises a first chalcogenide composition and the second memory element comprises a second chalcogenide composition.

5. The memory device of claim 4, wherein the first chalcogenide composition comprises at least one of As and Se.

6. The memory device of claim 1, further comprising:

a second isolation dielectric further formed over and covering the second protective dielectric insulating material.

7. The memory device of claim 6, wherein the second protective dielectric insulating material is formed on the second pair of sidewalls of the first memory element while not formed on sidewalls of the second memory element.

8. A memory device, comprising:

a semiconductor substrate;

a memory cell stack formed on the semiconductor substrate, the memory cell stack comprising;

a first memory element over the semiconductor substrate;

a second memory element formed over and overlapping the first memory element;

a first pair of sidewalls associated with the first memory element opposing each other, the first pair of sidewalls extending in a first direction;

a first protective dielectric insulating material formed on a lower portion of the first pair of sidewalls;

a second pair of sidewalls associated with the first memory element opposing each other;

a second protective dielectric insulating material formed on a lower portion of the second pair of sidewalls, the second protective dielectric insulating material extending in a second direction crossing the first direction associated with the first protective dielectric insulating material;

wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element; and

wherein the first protective dielectric insulating material is absent from sidewalls of the second memory element, the first memory element being closer to the semiconductor substrate than the second memory element.

9. The memory device of claim 8, further comprising an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.

10. The memory device of claim 8, wherein the second protective dielectric insulating material is formed on the second pair of sidewalls of the first memory element while not being formed on sidewalls of the second memory element.

11. The memory device of claim 8, wherein the second protective dielectric insulating material extends in the second direction and does not coterminate with the first memory element terminating in the second direction at the first pair of sidewalls.

12. The memory device of claim 8, wherein the memory device is a phase change memory device, and wherein the first memory element comprises a first chalcogenide composition and the second memory element comprises a second chalcogenide composition.

13. The memory device of claim 12, wherein the first chalcogenide composition comprises at least one of As and Se.