Method for fabricating a transistor device with a tuned dopant profile

• US 9,577,041 B2
• Filed: 02/25/2016
• Issued: 02/21/2017
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Bakhishev, Teymur, Pradhan, Sameer, Hoffmann, Thomas, Sonkusale, Sachin R.
• Primary Examiner(s): Payen, Marvin
• Application Number:
  US15/053,099
• Publication Number:
  US 20160172444A1
• Time in Patent Office: 362 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron.

Claims

1. A method for fabricating a transistor device having a gate, a channel, a source and a drain on either side of the channel, the channel having a tuned dopant profile, comprising:

defining an implant region;

performing a first implantation of a first dopant migration mitigating material into the implant region at a first preselected dopant migration mitigating energy and dose;

implanting a screening layer into the implant region at a preselected screening layer energy and screening layer dose, the screening layer defining a depletion width for the transistor channel when a voltage is applied to the gate;

wherein the first preselected dopant migration mitigating energy effects a placement of a peak of a dopant profile of the screening layer at a first location and a first thickness.

2. The method of claim 1, comprising:

implanting a threshold voltage set layer into the implant region at a preselected threshold voltage set layer energy and threshold voltage set layer dose;

wherein the preselected threshold voltage set layer energy and threshold voltage set layer dose effects a placement of the peak of a dopant profile of the threshold voltage layer to be different from the first location;

wherein the threshold voltage set layer is coextensive with the screening layer and abuts the source and drain and the screening layer extends laterally across the channel.

3. A method for fabricating a transistor device having a gate, a channel, a source and a drain on either side of the channel, the channel having a tuned dopant profile, comprising:

defining an implant region;

implanting a screening layer into the implant region at a preselected screening layer energy and screening layer dose, the screening layer defining a depletion width for the transistor channel when a voltage is applied to the gate;

depositing an epitaxial layer including a dopant migration mitigating material on the screening layer at a first preselected dopant migration mitigating thickness;

wherein a thickness of the epitaxial layer effects a placement of a peak of a dopant profile of the screening layer at a first location and a first thickness.

4. A method of claim 3, wherein the epitaxial layer comprises an epitaxial carbon-infused silicon.