Methods of manufacturing semiconductor devices

• US 9,577,076 B2
• Filed: 02/03/2015
• Issued: 02/21/2017
• Est. Priority Date: 05/07/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Keun-Hwi, Kim, Dong-Won, Harada, Yoshinao, Kang, Myung-Gil, Park, Jae-Young
• Primary Examiner(s): Nguyen, Duy T
• Assistant Examiner(s): AMER, MOUNIR S
• Application Number:
  US14/612,797
• Publication Number:
  US 20150325683A1
• Time in Patent Office: 749 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Abstract

In a method of manufacturing a semiconductor device, a plasma annealing and supplying a threshold voltage control gas onto a portion of a substrate is performed to form a fixed charge region including a fixed charge at a surface of the substrate. A MOS transistor is formed on the substrate including the fixed charge region. By the above processes, the threshold voltage of the MOS transistor may be easily controlled.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

performing a plasma annealing and supplying a threshold voltage control gas onto a portion of a substrate to form a fixed charge region including a fixed charge at a surface of the substrate; and

forming a MOS transistor on the substrate including the fixed charge region for controlling a threshold voltage of the MOS transistor, wherein the threshold voltage control gas has an atomic number smaller than that of an element of the substrate, and wherein the threshold voltage control as is supplied onto source and drain regions of the MOS transistor in the substrate, and wherein the fixed charge region is formed at the source and drain regions, and an edge portion of a channel region of the MOS transistor.

2. The method of claim 1, wherein the threshold voltage control gas is supplied onto the channel region of the MOS transistor in the substrate, and wherein the fixed charge region is formed at the channel region.

3. The method of claim 1, before performing the plasma annealing and supplying the threshold voltage control gas, further comprising forming a blocking layer pattern on the substrate.

4. The method of claim 1, wherein the threshold voltage control gas includes at least one selected from the group consisting of H, H₂, D₂ (deuterium), He, C and F.

5. The method of claim 1, wherein the plasma annealing is performed at a temperature of about 400 C. to about 600 C.

6. The method of claim 1, before performing the plasma annealing and supplying the threshold voltage control gas, further comprising forming an active fin and isolation layer on the substrate.

7. The method of claim 1, wherein forming the MOS transistor includes:

forming a gate structure including a gate insulation layer and a gate electrode sequentially stacked on the substrate including the fixed charge region; and

forming an impurity region at an upper portion of the substrate adjacent to the gate structure.

8. A method of manufacturing a semiconductor device, the method comprising:

forming an active fin and isolation layer on a substrate;

performing a plasma annealing and supplying a threshold voltage control gas onto the substrate to form a fixed charge region including a fixed charge at a surface of the substrate;

forming a gate structure including a gate insulation layer and a gate electrode sequentially stacked on the substrate including the fixed charge region for controlling a threshold voltage of the MOS transistor; and

forming an impurity region at an upper portion of the substrate adjacent to the gate structure, wherein the threshold voltage control gas has an atomic number smaller than that of an element of the substrate, and wherein the threshold voltage control gas is supplied onto source and drain regions of the MOS transistor in the substrate, and wherein the fixed charge region is formed at the source and drain regions, and an edge portion of a channel region of the MOS transistor.

9. The method of claim 8, wherein the substrate includes a first region for forming a first transistor of a first conductivity and a second region for forming a second transistor of a second conductivity, and wherein the method further comprises forming blocking layer pattern to cover the first or second region of the substrate so that the threshold voltage control gas is supplied onto an exposed portion of the substrate between the blocking layer pattern.

10. The method of claim 8, wherein the threshold voltage control gas is supplied onto the channel region of the MOS transistor in the substrate, and wherein the fixed charge region is formed at the channel region.

11. The method of claim 8, before performing the plasma annealing and supplying the threshold voltage control gas, further comprising forming a gate insulation layer on the substrate.

12. A method of manufacturing a semiconductor device, comprising:

performing a plasma annealing on a region of a substrate while supplying a threshold voltage supply gas to form a fixed charge region;

forming a transistor in the region of the substrate, the transistor including the fixed charge region, a threshold voltage of the transistor being controlled in accordance with the plasma annealing while supplying the threshold voltage supply gas, wherein the threshold voltage control gas has an atomic number smaller than that of an element of the substrate, and wherein the threshold voltage control gas is supplied onto source and drain regions of the transistor in the substrate, and wherein the fixed charge region is formed at the source and drain regions, and an edge portion of a channel region of the transistor.

13. The method of claim 12, wherein the fixed charge region is formed on a selected region of the substrate corresponding to the channel region of the transistor.

14. The method of claim 12, wherein performing the plasma annealing on a region of the substrate while supplying the threshold voltage supply gas to form the fixed charge region is performed through an opening formed as a result of the forming and removal of a dummy gate pattern.

15. The method of claim 12, wherein performing the plasma annealing on a region of the substrate while supplying the threshold voltage supply gas to form the fixed charge region is performed through a gate insulating layer of a gate of the resulting transistor.