Tunnel field effect transistors

• US 9,577,079 B2
• Filed: 12/17/2009
• Issued: 02/21/2017
• Est. Priority Date: 12/17/2009
• Status: Active Grant

• Current Assignee: Indian Institute of Technology Bombay, Infineon Technologies AG
• Original Assignee: Indian Institute of Technology Bombay, Infineon Technologies AG
• Inventors: Gossner, Harald, Rao, Ramgopal, Asra, Ram
• Primary Examiner(s): CHEN, DAVID Z
• Application Number:
  US12/641,088
• Publication Number:
  US 20110147838A1
• Time in Patent Office: 2,623 Days
• Field of Search: 257/E21.399, 257/458, 257/656, 257/E31.061, 257/E29.336, 257/E33.046, 257/345, 257/346, 257/347, 257/348, 257/349
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0895 Tunnel injectors
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66356 Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66977 Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/88 Tunnel-effect diodes

Abstract

Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a first channel region electrically coupled between the first source region and the first drain region, the first source region underlying a least a portion of the first channel region, and a first gate stack overlying the first channel region.

Claims

1. A semiconductor device comprising:

a first drain region of a first conductivity type disposed in a first region of a substrate;

a first source region of a second conductivity type disposed in said substrate, said second conductivity type being opposite said first conductivity type;

a first channel region electrically coupled between said first source region and said first drain region, said first source region directly underlying at least a first portion of said first channel region;

a first doped region of the first conductivity type disposed between the first source region and the first drain region, said first doped region contacting the first source region and the first drain region; and

a first gate stack overlying said first channel region, wherein the first source region is separated from the first gate stack by the first channel region and the first doped region is separated from the first gate stack by the first channel region, wherein the first source region and the first drain region are heavily doped, wherein the first channel region is lowly doped having the first conductivity type;

a tunnel junction at the intersection between the first source region and the first portion of the first channel region, wherein, the lowly doped first channel region has a lower dopant concentration than a dopant concentration of the heavily doped first source region so that, at the tunnel junction between the first source region and the first channel region, a net doping concentration varies abruptly from the heavily doped second conductivity type first source region to the lowly doped first conductivity type first channel region; and

a p/n junction at the intersection between the first source region and the first doped region.

2. The device of claim 1, further comprising a second source region of the second conductivity type disposed in the substrate and adjacent the first channel region.

3. The device of claim 1, wherein the first doped region is doped to a lower dopant concentration than a dopant concentration of the heavily doped first drain region.

4. The device of claim 1, wherein the first channel region comprises a semiconductor material different than a semiconductor material of the first source region.

5. The device of claim 1, wherein the first channel region comprises germanium.

6. The device of claim 5, wherein the germanium content is at least 15% by concentration.

7. The device of claim 1, wherein the first channel region comprises carbon.

8. The device of claim 7, wherein the carbon content is less than about 1%.

9. The device of claim 1, wherein the junction between the first channel region and the first source region is under strain.

10. The device of claim 9, wherein the strain increases a tunnel current at the junction.

11. The device of claim 1, wherein the first source region comprises a crystal orientation that enhances a tunnel current at the junction between the first channel region and the first source region, wherein the crystal orientation of the first source region is different than a crystal orientation within the substrate.

12. The device of claim 1, further comprising:

a second drain region of the second conductivity type disposed in a second region of the substrate;

a second source region of the first conductivity type disposed in said substrate;

a second channel region electrically coupled between said second source region and said second drain region, said second source region underlying a least a portion of said second channel region; and

a second gate stack overlying said second channel region.

13. The device of claim 12, wherein the first channel region and first source region are under a first type of strain, and wherein the second channel region and the second source region are under a second type of strain, wherein the first and the second types of strain are opposite types of strain.

14. The device of claim 1, wherein the first conductivity type is an n-type.

15. The device of claim 1, wherein a gate electrode in the first gate stack controls a tunneling current at the junction between the first channel region and the first source region.

16. The device of claim 1, wherein the first channel region is disposed above a top surface of the first source region and above a top surface of the first drain region.

17. The device of claim 1, wherein the p/n junction is a vertical p/n junction disposed directly below the first channel region.

18. The device of claim 1, wherein the first doped region is disposed under the first channel region.

19. The device of claim 18, wherein the first doped region separates the substrate from the first drain region.

20. The device of claim 18, wherein the substrate contacts the first drain region.

21. The device of claim 18, wherein the first source region contacts a well region of the substrate, and wherein the first source region is disposed between the first doped region and the well region, and wherein a doped trench region of the first conductivity isolates the first source region from an adjacent first source region.

22. The device of claim 18, wherein the first doped region extends further into the substrate than the first source region.

23. The device of claim 1, wherein the first source region contacts at least the first portion of said first channel region along a bottom surface of the first channel region.

24. The device of claim 1, wherein said first doped region directly underlies at least a second portion of said first channel region.

25. A semiconductor device comprising:

a first drain region of a first conductivity type disposed in a first region of a substrate;

a first source region of a second conductivity type disposed in said substrate, said second conductivity type being opposite said first conductivity type;

a second source region of the second conductivity type disposed above the first source region;

a first channel region electrically coupled between said first source region and said first drain region, said first source region directly underlying at least a first portion of said first channel region;

a first doped region of the first conductivity type underlying at least a second portion of said first channel region, said first doped region contacting the first source region and the first drain region;

a first gate stack overlying said first channel region, wherein the first source region is separated from the first gate stack by the first channel region and the first doped region is separated from the first gate stack by the first channel region, wherein the first source region and the first drain region are heavily doped, wherein the first channel region is lowly doped having the first conductivity type;

a tunnel junction at the intersection between the first source region and the first portion of the first channel region, wherein, the lowly doped first channel region has a lower dopant concentration than a dopant concentration of the heavily doped first source region so that, at the tunnel junction between the first source region and the first channel region, a net doping concentration varies abruptly from the heavily doped second conductivity type first source region to the lowly doped first conductivity type first channel region; and

a p/n junction at the intersection between the first source region and the first doped region, wherein, in the substrate, the first channel region contacts only the first source region, the first drain region, the first doped region, and the second source region.

26. The device of claim 25, wherein the first doped region is doped to a lower dopant concentration than a dopant concentration of the heavily doped first drain region.

27. The device of claim 25, wherein the first channel region comprises germanium.

28. The device of claim 25, wherein the first channel region comprises carbon.

29. The device of claim 25, wherein the junction between the first channel region and the first source region is under strain so as to increase a tunnel current at the junction.

30. The device of claim 25, wherein the first doped region separates the substrate from the first drain region.

31. The device of claim 25, wherein the p/n junction is a vertical p/n junction.

32. The device of claim 25, wherein the first source region contacts at least the first portion of said first channel region along a bottom surface of the first channel region.

33. A semiconductor device comprising:

a first drain region of a first conductivity type disposed in a first region of a substrate;

a first source region of a second conductivity type disposed in said substrate, said second conductivity type being opposite said first conductivity type;

a second source region of the second conductivity type disposed in said substrate and above the first source region;

a channel region electrically coupled between said first source region and said first drain region and between said second source region and said first drain region, said first source region directly underlying at least a first portion of said channel region, wherein the first source region, the first drain region, the second source region are heavily doped, and the channel region is lowly doped having the first conductivity type;

a horizontal tunnel junction is formed between said channel region and said first source region, wherein, at the horizontal tunnel junction between the first source region and the channel region, the lowly doped channel region has a lower dopant concentration than a dopant concentration of the heavily doped first source region so that, a net doping concentration varies abruptly from the heavily doped second conductivity type first source region to the lowly doped first conductivity type channel region;

a vertical tunnel junction is formed between said channel region and said second source region, wherein, at the vertical tunnel junction between the second source region and the channel region, a net doping concentration varies abruptly from the heavily doped second conductivity type second source region to the lowly doped first conductivity type channel region, and wherein the vertical tunnel junction is perpendicular to the horizontal tunnel junction;

a doped region of the first conductivity type underlying at least a second portion of said channel region, said doped region contacting the first source region and the first drain region, wherein, in the substrate, the channel region contacts only the first source region, the first drain region, the doped region, and the second source region; and

a gate stack overlying said channel region, wherein the first drain region, the first and second source regions, the channel region, the doped region, and the gate stack form a tunnel field effect transistor, wherein the first source region is separated from the gate stack by the channel region and the doped region is separated from the gate stack by the channel region.

34. The device of claim 33, wherein the doped region is doped to a lower dopant concentration than a dopant concentration of the heavily doped first drain region.

35. The device of claim 33, wherein the channel region is silicon-germanium, and wherein the first source region is silicon.

36. The device of claim 33, wherein the tunnel junction between the channel region and the first source region is under strain so as to increase a tunnel current at the tunnel junction.

37. The device of claim 33, wherein the doped region separates the substrate from the first drain region, and wherein the first source region and the doped region form a vertical p-n junction.

38. The device of claim 33, wherein the first source region contacts at least the first portion of said channel region along a bottom surface of the channel region.